LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 30

• Manufacturer Part Number: LAN91C96I_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Rev. 03-28-07
BYTE COUNT
Divided by two, it defines the total number of words, including the STATUS WORD, the BYTE COUNT
WORD, the DATA AREA and the CONTROL BYTE.
The receive byte count always appears as even, the ODDFRM bit of the receive status word indicates if
the low byte of the last word is relevant. The transmit byte count least significant bit will be assumed 0 by
the controller regardless of the value written in memory. The maximum size of the frame can be stored in 6
pages (256 bytes per page), the maximum BYTE COUNT number is 1536.
DATA AREA (in RAM)
The data area starts at offset 4 of the packet structure, and it can extend for up to 1531 bytes. The data
area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS,
followed by a variable length number of bytes.
On transmit, all bytes are provided by the CPU, including the source address. The LAN91C96I does not
insert its own source address. On receive, all bytes are provided by the CSMA side.
The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C96I. It is treated
transparently as data for both transmit and receive operations.
CONTROL BYTE (in RAM)
The CONTROL BYTE always resides on the high byte of the last word.
CONTROL BYTE is written by the CPU as:
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE.
If clear, the number of data bytes is even and the byte before the CONTROL BYTE is not transmitted.
CRC - When set, CRC will be appended to the frame. This bit has only meaning if the NOCRC bit in the
TCR is set.
For receive packets the CONTROL BYTE is written by the controller as:
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE.
If clear, the number of data bytes is even and the byte before the CONTROL BYTE should be ignored.
RECEIVE FRAME STATUS WORD (in RAM)
This word is written at the beginning of each receive frame in memory. It is not available as a register.
ALGN
ERR
BROD CAST
5
X
0
BADCRC
X
1
DATASHEET
4
ODD
ODD
HASH VALUE
ODDFRM
Page 30
CRC
0
3
0
0
TOOLN
0
0
G
2
0
Non-PCI Single-Chip Full Duplex Ethernet Controller
0
0
TOO
SHO
0
RT
1
0
For transmit packets the
MULT
CAST
SMSC DS – LAN91C96I