LAN91C96I_07 SMSC [SMSC Corporation], LAN91C96I_07 Datasheet - Page 51

• Manufacturer Part Number: LAN91C96I_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller
• Manufacturer: SMSC [SMSC Corporation]

Non-PCI Single-Chip Full Duplex Ethernet Controller
SMSC DS – LAN91C96I
I/O SPACE - BANK2
TX IDLE
TX IDLE
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C96I
regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory,
and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte
can be accessed through the Data Low or Data High registers. The order to and from the FIFO is
preserved. Byte and word accesses can be mixed on the fly in any order.
This register is mapped into two consecutive word locations to facilitate the usage of double word move
instructions. The DATA register is accessible at any address in the 8 through Ah range, while the number
of bytes being transferred are determined by A0 and nSBHE in local Bus mode.
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A
MASK bit being set will cause a hardware interrupt.
TX IDLE INT - Transmit Idle interrupt. Set when the transmit state machine is not active. This bit is used
under the condition where the TX FIFO is still NOT empty, the transmitter is disabled and the host wants to
determine when the transmitter is completed with the current transmit packet. This event usually happens
when the host wants to insert at the head of the transmit queue a frame for example.
Typical flow of events/Condition:
1.
2.
MASK
OFFSET
OFFSET
OFFSET
INT
INT
0
0
The transmit FIFO is not empty
The transmit DONE FIFO is either empty or not empty
C
C
D
ERCV
ERCV
ERCV
MASK
INT
INT
INT
0
0
INTERRUPT STATUS REGISTER
INTERRUPT MASK REGISTER
INTERRUPT ACKNOWLEDGE
MASK
EPH
EPH
INT
INT
0
0
REGISTER
NAME
DATASHEET
NAME
NAME
OVRN
OVRN
OVRN
MASK
RX_
RX_
RX_
INT
INT
INT
0
0
Page 51
ALLOC
ALLOC
MASK
INT
INT
0
0
EMPTY
READ/WRITE
EMPTY
EMPTY
WRITE ONLY
MASK
READ ONLY
INT
TX
INT
INT
TX
TX
1
0
TYPE
TYPE
TYPE
TX INT
TX INT
TX INT
MASK
0
0
SYMBOL
SYMBOL
SYMBOL
MSK
RCV INT
ACK
RCV INT
IST
MASK
0
0
Rev. 03-28-07