AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 93

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
9
The IC includes five NAND trees for continuity testing. It is also possible to place all the IO pins into the high-
impedance state. These modes are entered by asserting the following pins:
9.1
When in high impedance mode, all the signals on the IC are placed into the high impedance state.
9.2
There are five NAND trees in the IC. The following diagram shows how these are connected, using example signals
from NAND tree 1.
When in NAND tree mode, the five NAND tree output signals are enabled and the remaining signals are in high-
impedance mode. The following pins are not part of the NAND tree: RTCX_IN, RTCX_OUT, PWRGD, PCLK,
TEST#, PGNT#, and SERR#.
The following tables provide the signal order and output signal for each NAND tree.
NAND tree 1: output signal BCLK.
1
2
3
4
5
6
7
8
9
10 EKIRQ12
High Impedance ~TEST# & PWRGD & ~PGNT# & ~SERR#
NAND Tree
SA1
SA0
GPIO17
SD4
GPIO19
LA23
SD3
GPIO18
LA22
Test
Mode
BCLK signal
High Impedance Mode
NAND Tree Mode
LDRQ1#
GPIO17
…
VDD
SA1
SA0
Equation to enable mode
~TEST# & PWRGD & ~PGNT# &
11 SD2
12 IRQ10
13 LA21
14 SD1
15 SD0
16 IRQ11
17 LA20
18 IOCHRDY
19 GPIO25
20 IRQ12
21 LA19
22 GPIO21
23 SA16
24 IRQ15
25 LA18
26 GPIO20
27 IOW#
28 IRQ14
29 LA17
30 IOR#
Preliminary Information
NAND Tree Mode
…
31 CPUSLEEP# 41 LAD1
32 KA20G
33 MEMR#
34 MEMW#
35 KBRC#
36 GPIO9
37 LAD0
38 STRAPL2
39 SA14
40 SA15
SERR#
AMD-766
1
0
42 GPIO2
43 PRDY
44 LAD2
45 GPIO29
46 EKIRQ1
47 SA13
48 LAD3
49 GPIO28
50 GPIO23
TM
Peripheral Bus Controller Data Sheet
To BCLK pin
51 SA12
52 LFRAME#
53 GPIO31
54 SA10
55 SA11
56 LDRQ0#
57 GPIO30
58 SA9
59 LDRQ1#
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