AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 46

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
5.3.4
The legacy programmable interrupt controller (PIC) includes a master, which is accessed through ports 20h and 21h
and controls IRQ[7:0], and a slave, which is accessed through ports A0h and A1h and controls IRQ[15:8].
The following are all the PIC registers.
Offset
20h (master), Write only; D[4]=1b
A0h (slave)
21h (master), Write only
A1h (slave)
D[4:3] above refers to bits[4:3] of the associated 8-bit data field. Normally, once ICW1 is sent, ICW2, ICW3, and
ICW4 are sent in that order before any OCW registers are accessed.
ICW1: Initialization Command Word 1 Register
Fixed IO space; offset: 20h for master and A0h for slave; data bit[4] must be high. Write only.
ICW2: Initialization Command Word 2 Register
Fixed IO space; offset: 21h for master and A1h for slave. Write only.
ICW3M: Initialization Command Word 3 for Master Register
Fixed IO space; offset: 21h. Write only.
ICW3S: Initialization Command Word 3 for Slave Register
Fixed IO space; offset: A1h. Write only.
ICW4: Initialization Command Word 4 Register
Fixed IO space; offset: 21h for master and A1h for slave. Write only.
Bits
Bits
Bits
Bits
7:5
7:0
7:3
2:0
7:5
3:2
4
3
2
1
0
4
1
0
Legacy Programmable Interrupt Controller (PIC) Registers
Description
A[7:5]: interrupt vector address. These bits are not implemented.
This should always be high.
LTIM: level triggered mode. This bit is not implemented; PORT4D0 controls this function instead.
ADI: call address interval. This bit is not implemented.
SNGL: single mode. This bit must be programmed low to indicate cascade mode.
IC4: ICW4 needed. This bit must be programmed high.
Description
SLAVES[7:0]. These bits must always be programmed to 04h.
Description
Reserved (must be programmed to all zeros).
ID[2:0]. These bits must always be programmed to 02h.
Description
Reserved (must be programmed all zeros)
SFNM. Special fully nested mode. This bit is normally programmed low.
BUFF and MS. These two are normally programmed to 00b for non-buffered mode.
AEOI. Auto EOI. This bit is ignored; the IC only operates in normal EOI mode (this bit low).
UPM. x86 mode. This bit is ignored; the IC only operates in x86 mode (this bit high).
Access type
Write only; D[4:3]=00b
Read-write; D[4:3]=01b Operation command word 3 (OCW3)
Write only
Write only
Read-write
Register
Initialization command word 1 (ICW1)
Operation command word 2 (OCW2)
Initialization command word 2 (ICW2)
Initialization command word 3 (ICW3)
Initialization command word 4 (ICW4)
Operation command word 1 (OCW1)
Preliminary Information
AMD-766
TM
Peripheral Bus Controller Data Sheet
46