AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 28

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
4.6.1.5.2
C3A50 specifies the definition of these transitions as enables for the following signals: CPURST#, SUSPEND#,
CPUSLEEP#, PCISTOP#, CPUSTOP#, DCSTOP#, CACHE_ZZ. Any of these signals may be enabled for the
transition to any of C2, C3 or POS. The transition to C2, C3, or POS occurs as follows, for each of the enabled pin
controls:
4.6.1.5.3
The following is the resume sequence from C2, C3, and POS, once an enabled resume event occurs. These resume
events are enabled by PM16 and, in the case of C3, PM04[1]. Here is the resume sequence, once an enabled resume
event occurs, if the SUSPEND# pin is enabled in C3A50:
The following is the resume sequence, once an enabled resume event occurs, if the SUSPEND# pin is not enabled,
but any of DCSTOP#, PCISTOP#, CPUSLEEP, and CPUSTOP# are enabled in C3A50:
The following is the resume sequence, once an enabled resume event occurs, if the SUSPEND#, PCISTOP#,
CPUSTOP#, CPUSLEEP, and DCSTOP# pins is not enabled in C3A50:
Processor initiation. The transition to C2 is initiated by reading PM14; the transition to C3 is initiated by
reading PM15; the transition to POS is initiated by writing the appropriate value to PM04[SLP_EN, SLP_TYP].
Stop-grant. The IC asserts STPCLK# and waits for the stop-grant cycle from the host (a PCI special cycle as
specified by C3A41[STPGNT]) to complete.
PICCLK. If going into POS and C3A50[APIC_POSEN] is low, then PICCLK held low after stop-grant.
CACHE_ZZ. At least four PCLK cycles after stop-grant, CACHE_ZZ is asserted.
DCSTOP#. At least eight PCLK cycles after stop-grant, DCSTOP# is asserted.
CPUSLEEP#. At least 64 PCLK cycles after stop-grant, CPUSLEEP# is asserted.
CPUSTOP# and PCISTOP#. At least 68 PCLK cycles after stop-grant, CPUSTOP# and PCISTOP# are asserted.
SUSPEND#. At least 80 PCLK cycles after stop-grant, SUSPEND# is asserted.
SUSPEND#. Immediately after the resume event, SUSPEND#, CPUSLEEP# and STPCLK# are deasserted
within 100 nanoseconds of each other. If CPURST# is enabled to be asserted by C3A50, it is asserted as well. If
resuming from POS and C3A50[APIC_POSEN] is low, then PICCLK becomes active at this time.
CPUSTOP# and PCISTOP#. 17 to 18 milliseconds after SUSPEND#, CPUSTOP# and PCISTOP# are
deasserted.
DCSTOP#. 700 to 800 microseconds after CPUSTOP# and PCISTOP#, DCSTOP# is deasserted.
CACHE_ZZ. 240 to 250 microseconds after DCSTOP#, CACHE_ZZ is deasserted.
CPURST#. 4 to6 PCLK cycles after CACHE_ZZ, CPURST# is deasserted (if it was asserted).
CPUSTOP# and PCISTOP#. CPUSTOP# and PCISTOP# are deasserted immediately after the resume event. If
resuming from POS and C3A50[APIC_POSEN] is low, then PICCLK becomes active at this time.
DCSTOP#. 700 to 800 microseconds after the resume event, DCSTOP# and CPUSLEEP# are deasserted.
CACHE_ZZ. 240 to 250 microseconds after DCSTOP#, CACHE_ZZ is deasserted.
STPCLK#. 4 to 6 PCLK cycles after CACHE_ZZ, STPCLK# is deasserted.
CACHE_ZZ. At least 4 PCLK cycles after the resume event, CACHE_ZZ is deasserted. If resuming from POS
and C3A50[APIC_POSEN] is low, then PICCLK becomes active at this time.
STPCLK#. 4 to 6 PCLK cycles after CACHE_ZZ, STPCLK# is deasserted.
Transitions From C2, C3 And POS To FON
Transitions From FON To C2, C3 And POS
Preliminary Information
AMD-766
TM
Peripheral Bus Controller Data Sheet
28