AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 51

no-image

AMD-766AC

Manufacturer Part Number
AMD-766AC
Description
Peripheral Bus Controller
Manufacturer
AMD [Advanced Micro Devices]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AMD-766AC
Manufacturer:
AMD
Quantity:
20 000
Part Number:
AMD-766ACT
Manufacturer:
MICROHIP
Quantity:
109
Part Number:
AMD-766ACT
Manufacturer:
AMD
Quantity:
2 700
Part Number:
AMD-766ACT
Manufacturer:
AMD
Quantity:
20 000
23167B – March 2001
C1A18: EIDE Controller Secondary Command Base Address
Configuration space; function 1; offset: 1B-18h. Default: 0000 0171h. Read-write. When C1A08[10] is low, the
secondary port is in compatibility mode and this register is ignored and not visible (reads as 0h).
31:3
BASE
BASE[31:3] Port Address. These bits specify an 8-byte IO address space that maps to the ATA-compliant
command register set for the secondary port (legacy IO space 170h through 177h).
C1A1C: EIDE Controller Secondary Control Base Address
Configuration space; function 1; offset: 1F-1Ch. Default: 0000 0375h. Read-write. When C1A08[10] is low, the
secondary port is in compatibility mode and this register is ignored and not visible (reads as 0h).
31:2
BASE
BASE[31:2] Port Address. These bits specify a 4-byte IO address space that maps to the ATA-compliant control
register set for the secondary port (legacy IO space 376h). Note: Only byte 2 of this space is used.
C1A20: EIDE Controller Bus Master Control Registers Base Address
Configuration space; function 1; offset: 23-20h. Default: 0000 CC01h. Read-write.
31:4
BASE
BASE[31:4] Port Address. These bits specify the 16-byte IO address space that maps to an EIDE register set that is
compliant with the SFF 8038I rev. 1.0 specification (Bus Master Programming Interface for IDE ATA Controllers),
IBMx.
C1A2C: EIDE Controller Subsystem ID and Subsystem Vendor ID Register
Configuration space; function 1; offset: 2F-2Ch. Default: 0000_0000h. Read-only.
31:16
SSID
SSVENDORID and SSID. Subsystem vendor ID and subsystem ID registers. This register is write accessible
through C0A70.
C1A3C: EIDE Controller Interrupt Line, Interrupt Pin, Min Grant, Max Latency Register
Configuration space; function 1; offset: 3F-3Ch. Default: 0000 0000h.
31:24
MAX LATENCY
INTERRUPT LINE. This register is either read-write or read-only based on the state of C1A08[10,8]. When either
C1A08[8] or C1A08[10] is high, then this is a read-write register. When they are both low, then it is a read-only
register, reading 00h. This register controls no hardware.
INTERRUPT PIN. Read only. When either C1A08[8] or C1A08[10] is high, then field reads 01h. When they are
both low, it reads 00h.
MIN GNT.
MAX LATENCY. Read only. These bits are fixed at their default values.
Read only. These bits are fixed at their default values.
23:16
MIN GNT
Preliminary Information
15:0
SSVENDORID
15:8
INTERRUPT PIN
AMD-766
TM
Peripheral Bus Controller Data Sheet
7:0
INTERRUPT LINE
3:0
‘b0001
2:0
Reserved.
1:0
Reserved.
51

Related parts for AMD-766AC