AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 17

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
The inactive time between IO commands is specified by C0A40[IORT] to be either 5.5 or 13.5 BCLK cycles.
However, if there is a multi-byte PCI cycle that is converted into multiple ISA cycles, then there is only 1.5 BCLK
cycles between each of these, regardless as to the state of C0A40[IORT].
4.3.2
The IC includes a standard LPC controller with two DMA request pins. The LPC bus may be the default path for
subtractive cycles based on the state of C0A48[SUB]. The LPC bus may be the path for ROM BIOS transactions
based on the state of C0A43 and the ISABIOS pin. Additional LPC address space is specified by C3A[5C:51].
All LPC master and DMA cycles are routed to the PCI interface. LPC does not support peer-to-peer transfers to
internal or external LPC devices.
The IC supports LPC DMA cycle sizes of 8- and 16-bits and master cycle sizes of 8-, 16-, and 32- bits. The IC
supports LPC DMA cycles with addresses of up to 16MB (24 address bits) and LPC master cycles with addresses of
up to 4GB (32 address bits). LPC master cycles must be naturally aligned (i.e., 16-bit master cycles must start at an
address where A[0]=0b and 32-bit master cycles must start at an address where A[1:0]=00b).
The inactive time between IO commands is specified by C0A40[IORT] to be either 22 or 54 PCLK cycles. However,
if there is a multi-byte cycle that is converted into multiple LC cycles, then there is only 2 PCLK cycles between each
of these, regardless as to the state of C0A40[IORT].
Any LPC target cycles in which there is no response on the LPC bus are responded to as follows: writes are dropped
(PCI cycle ends normally); reads return all 1’s.
4.3.3
The IC includes the following legacy support logic:
PORT61 and PORT92 legacy registers.
FERR# and IGNNE interrupt logic.
PORT4D0 legacy interrupt edge-level select logic.
PORTCF9 reset logic.
Legacy DMA controller.
Legacy programmable interval timer.
LPC Interface
Legacy and Miscellaneous Support Logic
Preliminary Information
AMD-766
TM
Peripheral Bus Controller Data Sheet
17