AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 32

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
Fixed address spaces.
Relocatable address spaces.
Note: C1A10, C1A14, C1A18, and C1A20 are only used when the IDE controller is in native mode as specified by
C1A08.
The following are register behaviors found in the register descriptions.
Type
Read or read only
Write
Set by hardware
Write 1 to clear
Write 1 only
Write once
FEC0_0000 to
1F0-1F7, 376
170-177, 376
Base address
FEC0_001F
4D0-4D1
register
C1A1C
A0-A1
C0-DF
C1A10
C1A14
C1A18
C1A20
C3A58
C4A10
Port(s)
60, 64
00-0F
80-8F
F0-F1
20-21
40-43
70-73
CF9
61
92
Mnemonic
PORT4D0
PORTCF9
Mnemonic
PORTxxx
PORTxxx
PORTxx
PORTxx
PORTxx
PORTxx
PORT61
PORTxx
PORT92
PORTxx
PORTxx
PORTxx
USBxxx
RTCxx
IOAxx
PMxx
IBMx
None
None
None
None
Description
Capable of being read by software. Read only implies that the register cannot be written to by
software.
Capable of being written by software.
Register bit is set high hardware.
Software must write a 1 to the bit in order to clear it. Writing a 0 to these bits has no effect.
Software may set the bit high by writing a 1 to it. However subsequent writes of 0 have no
effect. RESET# must be asserted in order to clear the bit.
After RESET#, these registers may be written to once. After they are written, they become
read only until the next RESET# assertion.
Memory mapped IOAPIC register set
Memory mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
IO mapped
Type
Type
Preliminary Information
Function
Slave DMA controller
Master interrupt controller
Programmable interval timer
USB keyboard emulation address
AT Compatibility Register
Real-time clock and CMOS RAM
DMA page registers
System control register
Slave interrupt controller
Master DMA controller
Floating point error control
Secondary IDE drives (not used when in native mode)
Primary IDE drives (not used when in native mode)
EISA-defined level-triggered interrupt control registers
System reset register
(bytes)
Size
256 System management IO register space
4K
16
8
4
8
4
Function
Pointer to primary port IDE command space
Pointer to primary port IDE control space
Pointer to secondary port IDE command space
Pointer to secondary port IDE control space
IDE controller bus master control registers
USB IO register space
AMD-766
TM
Peripheral Bus Controller Data Sheet
32