AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 69

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
PM02: Power Management 1 Enable Register
IO mapped (base pointer: C3A58); offset: 03-02h. Default: 0000h. Read-write.
These bits work in conjunction with the corresponding bits in PM00 to generate SCI or SMI interrupts.
15:11
Reserved
7:6
Reserved
TMR_EN. ACPI timer SCI enable. 1=Enable an SCI interrupt when PM00[TMR_STS] is set high. Note: This
results in an SCI interrupt, regardless as to the state of PM04[SCI_EN].
GBL_EN. Global SCI enable. 1=Enable an SCI interrupt when PM00[GBL_STS] is set high. Note: This results in
an SCI interrupt, regardless as to the state of PM04[SCI_EN].
PWRBTN_EN. Power button SCI/SMI enable. 1=Enable either an SCI or an SMI interrupt (based on the state of
PM04[SCI_EN]) when PM00[PWRBTN_STS] is set high.
SLPBTN_EN. Sleep button SCI/SMI enable. 1=Enable either an SCI or an SMI interrupt (based on the state of
PM04[SCI_EN]) when PM00[SLPBTN_STS] is set high.
RTC_EN. Real time clock alarm SCI/SMI enable. 1=Enable either an SCI or an SMI interrupt (based on the state
of PM04[SCI_EN]) when PM00[RTC_STS] is set high.
PM04: Power Management 1 Control Register
IO mapped (base pointer: C3A58); offset: 05-04h. Default: 0000h.
15:14
Reserved
SCI_EN. SCI-SMI select. Read-write. Selects the type of interrupt generated by power management events.
Certain power management events may be programmed individually to generate SMI interrupts independent of the
state of this bit. Also, TMR_STS and GBL_STS always generate SCI interrupts regardless as to the state of this bit.
See section 4.6.1.1 for details.
BM_RLD. Bus master reload. Read-write. 1=Enables PM00[BM_STS] to resume from C3.
GBL_RLS. Global release. Read; write 1 to set; cleared by hardware. When this bit is set high, the hardware sets
PM28[BIOS_STS] high. GBL_RLS is cleared by the hardware when PM28[BIOS_STS] is cleared by software.
SLP_TYP. Sleep type. Read-write. Specifies the type of sleep state the system enters when SLP_EN is set high.
SLP_EN. Sleep enable. Write 1 only; reads back as 0. Writing a 1 to this bit causes the system to sequence into the
sleep state specified by SLP_TYP.
0
1
0
1
2-4
5
6
7
FON, S0. Full on.
POS, S1. Power on suspend.
Reserved.
STR, S3. Suspend to RAM.
STD, S4. Suspend to disk.
SOFF, S5. Soft off.
SMI interrupt.
SCI interrupt.
13
SLP_EN
5
GBL_EN
12:10
SLP_TYP
4:1
Reserved
Preliminary Information
9:3
Reserved
AMD-766
10
RTC_EN
TM
2
GBL_RLS BM_RLD
Peripheral Bus Controller Data Sheet
SLPBTN_EN PWRBTN_EN
9
1
8
0
TMR_EN
0
SCI_EN
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