AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 8

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
3.2
Pin name and description
AD[31:0]. Address-data bus.
CBE_L[3:0]. Command-byte enable bus.
DEVSEL#. Device select.
FRAME#. Frame signal.
IDSEL. Identification select signal.
IRDY#. Master ready signal.
PAR. Parity signal.
PCIRST#. PCI reset. This is the system reset signal for logic that is
powered by the system’s main power supplies.
PCLK. 33 MHz PCI clock. This is required to remain active during reset
and when the IC enters the power-on suspend state (POS).
PGNT#. Master grant signal.
PIRQ[A, B, C, D]#. PCI interrupt requests. Only PIRQD# is an output
as well as an input; it may be driven active by the USB interrupt. The
other three pins are inputs only.
PREQ#. Master request signal.
SERR#. PCI system error signal. This may be asserted by the system to
indicate a system error condition. If enabled by RTC70[7], an NMI
interrupt may be generated.
STOP#. Target abort signal.
TRDY#. Target ready signal.
3.3
Pin name and description
A20M#. Address bit[20] mask to the processor. This output is a logical
OR of the KA20G pin from the keyboard controller and PORT92[A20EN].
CPURST#. CPURST#. Reset to the processor. This is the reset to
processor(s). See sections 4.1.1 and 4.6.1.5.1.
FERR#. Floating-point error from the processor. The processor asserts
this signal to indicate a floating-point error has occurred. This is used to
create IRQ13 to the PIC and IOAPIC.
IGNNE#. Ignore numeric error to the processor.
INIT#. Initialization interrupt to the processor.
INTR. Interrupt request to the processor.
NMI. Non-maskable interrupt request to the processor.
PICCLK. Interrupt message bus clock for the IOAPIC. This is controlled
through C0Ax4B[APICCKS]. During POS, PICCLK may be selected to
either be active or forced low by C3A50[APIC_POSEN].
PICD0# and PICD1#. Interrupt message bus data bits 1 and 0 for the
IOAPIC.
SMI#. System management interrupt to the processor.
STPCLK#. Processor stop-grant request.
WSC#. Write snoop complete. This signal is used to guarantee the most
recent PCI bus writes from the IC to system memory are visible to the host.
See section 4.3.2 for more details. This signal requires an external pull-up
resistor with a value between 10K to 200K ohms.
PCI Interface
Processor Interface
Preliminary Information
AMD-766
TM
IO cell
Output VDD3 3-state 3-state 3-state
Output VDD_
Output VDD3
IO cell
IO-PU VDD3 3-state 3-state 3-state
IO-PU VDD3 3-state 3-state 3-state
IO-PU VDD3 3-state 3-state 3-state
IO-PU VDD3 3-state 3-state 3-state
IO-PU VDD3 3-state 3-state 3-state
Input-
Input
Input
Input
IOD-
Input
IOD
IOD
IOD
type
type
w/H
OD
OD
OD
OD
OD
OD
OD
OD
PU
PU
IO
IO
Peripheral Bus Controller Data Sheet
VDD3 3-state 3-state 3-state
VDD3 3-state 3-state 3-state
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3 3-state 3-state 3-state
VDD3
VDD3
VDD3 3-state 3-state 3-state
VDD3 3-state 3-state 3-state
VDD3
VDD3
VDD3
VDD3 3-state 3-state 3-state
VDD3 3-state 3-state 3-state
VDD3 3-state 3-state Active
VDD3 3-state 3-state 3-state
Power
SOFT
Power
plane
plane
During
During
Func.
Reset
Reset
High
Low
Low
Low
Low
-
-
-
-
-
-
Reset
Reset
Func.
Func.
High
High
Post
Post
Low
Low
-
-
-
-
-
-
3-state
High
High
POS
POS
Low
low
-
-
-
-
-
-
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