AMD-762 Advanced Micro Devices, AMD-762 Datasheet
AMD-762
Related parts for AMD-762
AMD-762 Summary of contents
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... AMD-762™ System Controller Publication # 24416 Rev: C Issue Date: December 2001 Data Sheet ...
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... AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo and combinations thereof, AMD Athlon, AMD-760, AMD-761, AMD-762, AMD-766, and AMD-768 are trademarks of Advanced Micro Devices, Inc. Alpha is a trademark of Digital Equipment Corporation. ...
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... PCI Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 Memory Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.3 PCI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.4 PCI Parity/ECC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.5 PCI Accesses by an Initiator . . . . . . . . . . . . . . . . . . . . . 19 Table of Contents Preliminary Information AMD-762™ System Controller Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Legacy Mode—Single PCI Bus Southbridge . . . . . . . . . . . . . 16 Southbridge with an Integrated PCI-PCI Bus Bridge Arbitration Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... AMD-762™ System Controller Data Sheet 2.4 Accelerated Graphics Port (AGP) 2.5 System Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.6.1 Full-On (C0 2.6.2 Halt (C1 2.6.3 Throttling with STPCLK# Assertion . . . . . . . . . . . . . . . 27 2.6.4 Power-On Suspend (S1 2.6.5 Suspend to RAM (S3 Test 3.1 Board (Three-State) Test Mode 3.1.1 Board Test Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . 36 3.2 NAND Tree Test Mode 3 ...
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... Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Data Terminology 103 Abbreviations and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . 104 Related Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table of Contents Preliminary Information AMD-762™ System Controller Data Sheet Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . . 62 AGP Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PCI Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AMD Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Bus Architecture ...
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... AMD-762™ System Controller Data Sheet vi Preliminary Information 24416C—December 2001 Table of Contents ...
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... AMD-760MP™ Chipset System Block Diagram (33-MHz PCI) 6 Push-Pull Transmission Line Example . . . . . . . . . . . . . . . . . . . 9 Dummy Load with External Compensation Resistors . . . . . . . 9 AMD-762™ System Controller Connection to DDR DIMMs . 12 DRAM Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 System Clocking with 66-MHz PCI Primary Bus . . . . . . . . . . 23 System Clocking with 33-MHz PCI Bus . . . . . . . . . . . . . . . . . . 24 Power Management Signal Connections ...
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... AMD-762™ System Controller Data Sheet viii Preliminary Information 24416C— December 2001 List of Figures ...
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... List of Tables Preliminary Information Total Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AMD Athlon Processor System Bus NAND Tree Ordering . . . 38 AMD-762 System Controller AGP NAND Tree Ordering . . . . . 41 AMD-762 System Controller DDR NAND Tree Ordering . . . . 42 AMD-762 System Controller PCI NAND Tree Ordering . . . . . 44 Clocking Options in PLL Bypass Test Mode . . . . . . . . . . . . . . . 45 Clock Output Test Mode Options ...
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... AMD-762 System Controller Pin Functional Grouping ( AMD-762 System Controller Pin Functional Grouping ( AMD-762 System Controller Pin Functional Grouping ( AMD-762 System Controller Pin Functional Grouping ( AMD-762 System Controller Pin Functional Grouping ( Signal Descriptions Table Definitions . . . . . . . . . . . . . . . . . . . . 81 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Initialization Pinstrapping ...
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... Added AMD-768 peripheral bus controller throughout as the Southbridge device for the MPX Dec./2001 C chipset. June/2001 B-1 Package name in datasheet corrected from PBGA to CCGA. June/2001 B Initial public release. Nov./2000 A Initial NDA release. Revision History Preliminary Information AMD-762™ System Controller Data Sheet Description xi ...
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... AMD-762™ System Controller Data Sheet xii Preliminary Information 24416C—December 2001 Revision History ...
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... AMD-760MP chipset consists of the AMD-762 system controller in a CCGA package and the AMD-766™ peripheral bus controller. The AMD-762 system con t rolle the AMD At hlon system bus, system memory controller, Accelerated Graphics Port (AGP) controller, and Peripheral Component Interconnect (PCI) bus controller ...
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... Controller Data Sheet, order# 23167. For a description of the AMD-768 perip controlle r , see AMD-768™ Peripheral Bus Controller Data Sheet, order# 24467. Key features of the AMD-762 system controller are provided in this section. 1 Athlon™ System Buses The AMD Athlon system buses have the following features: ...
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... Read Line (MRL), Memory Read Multiple (MRM), and Memory-Write-and-Invalidate (MWI) Chapter 1 Preliminary Information memory-timing Programmable refresh rate CAS-before-RAS Populated banks only Automatic refresh of idle slots—improves bus availability for memory access by the processor or system Features AMD-762™ System Controller Data Sheet parameters and 3 ...
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... Power Management The power management features include the following: n Compliance support for both Advanced Configuration and Power Interface (ACPI) and Microsoft management n The AMD-762 system controller supports the following power states: • • 4 Preliminary Information Compliance with Accelerated Graphics Port Interface Specification, Revision 2 ...
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... PCI Bus (Primary) 64 bit 66/33 MHz AMD-768™ Peripheral Bus Southbridge LAN Controller Ethernet LPC USB EIDE PCI Bus (Secondary) 32 bit 33 MHz Features AMD-762™ System Controller Data Sheet DDR SDRAM DRAM Graphics DRAM Up to two additional 66-MHz PCI bus masters SCSI BIOS 5 ...
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... AMD-762™ System Controller Data Sheet 64-bit data + 8-bit ECC 13-bit SADDIN + 13-bit SADDOUT System Controller SERR# SBREQ# SBGNT# WSC# DCSTOP# System Management, Reset, Initialize, Interrupts Figure 2. AMD-760MP™ Chipset System Block Diagram (33-MHz PCI) 6 Preliminary Information AMD Athlon™ AMD Athlon ...
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... SADDIN and SADDOUT bus split ion sch rovides parallelism between the various buses and facilitates pipeline flow or memory requests and responses. Chapter 2 Preliminary Information AMD-762™ System Controller Data Sheet Functional Operation 7 ...
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... AMDAthlon™ System Bus Design Guide, order# 22666. 2.1.3 Push-Pull Compensation The AMD-762 system con t roller p rovides push-pull drive r configuration. The push-pull driver scheme implements drivers with a user-defined output impedance. This feature allows the point-to-point signals to be source terminated without any external devices, greatly simplifying layout and reducing cost ...
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... The drive strength is changed in small steps when no data is being driven. Refer to Figure Figure 4. Dummy Load with External Compensation Resistors Chapter 2 Preliminary Information AMD-762™ System Controller Data Sheet Transmission Line + VTT INP INN Dummy Driver Functional Operation ...
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... SDRAM DIMMs. The AMD-762 system controller memory interface is designed to support regist e red DDR DIMMs fou r regis DIMMs can be supported by the AMD-762 system controller. The AMD-762 system controller supports 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit DDR devices. Device widths of x4, x8, and x16 are supported ...
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... The maximum address space supported by the AMD-762 system controller is 4 Gbytes. Support of four regist DIMMs is accomplished by the AMD-762 syst e m con t r olle r ’s eight DDR ch ip -se lect pins (CS[7:0]#), which allow DIMMs with two ch ip sele illustrated in Figure 5 on page 12. In this example, each DIMM contains two physical DRAM banks, thus two chip selects are routed to the DIMM ...
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... AMD-762™ System Controller Connection to DDR DIMMs 2.2.1 DRAM Refresh The AMD-762 system controller keeps track of when each of CS independently. Refresh is only performed on rows that are populated ...
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... DQS signals are driven by the device that is currently driving the data bus. The AMD-762 system controller provides one DQS pin per byt e when using x8 and x16 DIMMs, or one per nibble when using x4 DIMMs. The Data Mask (DM) pins provide the additional DQS strobe function when accessing a x4 DIMM ...
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... Because the system clock is generated by a PLL in the AMD-762 system controller that is already compensated for PVT syst em clock period is independent of PVT. Therefore, the clock period can be assumed constant, and can be used to correlate the PDL values to units of time ...
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... PCI-initiator transactions. When the processor drives an I/O cycle to an address other than the AMD-762 system con addresses, the AMD-762 system controller passes the I/O cycle to the PCI bus and responds to the CPU only after the PCI cycle completes ...
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... PCI bus among itself on behalf of the processors, the Southbridge, and other PCI initiators AMD-762 seve grant pins and a dedicated grant pin for the Southbridge when opera t ing in legacy mode. The request/grant pairs used depend on the system configuration supported as described in the following sections ...
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... PCI bus that supports up to seven slots that can be used for less bandwidth-intensive peripherals. In this system configura t ion, the South br i dge connect the AMD-762 system controller’s REQ[0]# and GNT[0]# request/grant pair, and the two optional slots on the primary bus connect to the REQ[2:1]# and GNT[2:1]# pairs ...
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... AMD-762™ System Controller Data Sheet 2.3.3 PCI Configuration Th e AMD-762 syst em con t r olle r uses PCI configu anism # all tions ava for interaction with the processor, DRAM, and the PCI bus. This mech define PCI Local Bus Specificat ion, Revision 2 ...
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... FRAME# and pla AD[31:00] (note that the AMD-762 system controller supports a maximum a dd ress spa bits). The AMD-762 system controller decodes the address. If the address is within the gion PCI Top (Dev 0:F0:0x9C), the AMD-762 system controller accepts the cycle and responds as a PCI target by asser t ing DEVSEL# ...
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... Freedom from the coherency requirements of PCI, which eliminates the latency resulting from cache snooping. n Full PCI 2.2 capability, which enables the AMD-762 system controller to pass programming information from the processor to the graphics adapter Graphics Address Remapping Table (GART). ...
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... Low-priority reads push low-priority writes, meaning that a write request is serviced before a subsequently received read request is serviced. n Low-priority writes can pass low-priority reads, meaning that a write request can be serviced before a previously received read request. Chapter 2 Preliminary Information AMD-762™ System Controller Data Sheet Functional Operation 21 ...
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... Southbridge as described in the following sections. 66-MHz PCI Bus The highest performance option supports a 66-MHz primary PCI bus AMD-762 syst em controller , with a 33-MHz secondary PCI bus controlled by an AMD-768 peripheral bus controller’s PCI to PCI bridge. This mode also provides up to two optional slots for 66-MHz peripherals ...
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... Southbridge and the two PCI bus slots in this mode 33-MHz-only card is inserted in one of the 66-MHz PCI slots, then the M66EN signal is deasserted, which causes the AMD-762 system controller to drive 33 MHz on the PCI_66CLK[2:0] pins. The 66-MHz PCI mode is illustrated in Figure 7. ...
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... AMD-762™ System Controller Data Sheet The AMD-762 system controller implements three int e rna l PLLs to control clock skew on-chip for the SYSCLK, AGPCLK, and PCICLK domains. An external feedback path is required on the motherboard for the 66-MHz PCI PLL when operating in 66-MHz mode. This requires the PCI_66CLK[0] output pin to be connected back into the AMD-762 system controller’ ...
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... Power Management Th e AMD-762 system con Adva Configuration Power Interface (ACPI) specification, On-Now, and PC 99 requirements through a handshake mechanism with the processor. The ACPI-defined registers required for processor owe ...
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... In general, the processor initiates for a disconnect with a special cycle, and AMD-762 system controller may or may not actually disconnect rocessor with the connect/discon ocol AMD- connect/discon n ect the process of ent e r ing and exiting certain ACPI states ...
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... AMD-762 system con t rolle r disconnects the processor and places system memory into self-refresh mode before passing specia l cycle to the PCI Bus. If the AMD-762 syst em controller detects a PCI DMA master transaction that needs a snoop, then the processors are connected, DRAM is taken out of self-refresh mode, and the probe cycle(s) are initiated on the AMD Athlon processor system buses ...
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... AMD Athlon processor system bus following the completion of the probe. If the processors start sending non-NOP AMD Athlon processor system bus cycles whil the AMD-762 system oll e r transitions to the full-on state. 2.6.4 ...
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... DRAM in self-refresh mode. The DRAM controller initiates self-refresh, then acknowledges to the power management logic. • 6. The AMD-762 system controller issues a Stop Grant special cycle on the PCI bus. 7. The Southbridge detects the Stop Grant special cycle on the PCI bus and asserts the DCSTOP# signal. ...
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... S1 state. 2.6.5 Suspend to RAM (S3) The S3 state is similar to S1. However, power is removed from most AMD-762 sys controller, DRAM, and a portion of the Southbridge the 30 Preliminary Information Stop Grant Special Cycle ...
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... DCSTOP#. After entering S3 state wit h DCSTOP# assertion, the Southbridge asserts the RESET# signal, which causes the AMD-762 system controller to gate off its I/O rings ccom mod vol ove AMD Athlon processor system bus, PCI bus, and AGP bus ...
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... AMD-762™ System Controller Data Sheet 6. The AMD-762 system controller issues a Stop Grant special cycle on the PCI bus. 7. The Southbridge asserts DCSTOP#. The AMD-762 system controller described in “S1 Sequence” on page 28, including gating most of the internal clocks off. The DDR output clocks (CLKOUT[5:0], CLKOUT[5:0]#) continue running for an additional six clock periods from the assertion of RESET# ...
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... Suspend to RAM System Timing Diagram Example Chapter 2 Preliminary Information 30– CPU Disconnect Occurs Here Self-Refresh Functional Operation AMD-762™ System Controller Data Sheet 20–50 ms 1.5–2 ms 30–60 ms Running Full Speed Running Full Speed Running Full Speed Running Full Speed 33 ...
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... PCIRST# (the RESET# pin on the AMD-762 system controller AMD-762 system con t r olle memory controller configuration registers, which allows BIOS to immedia t ely access memory to ret r ieve and rest ore the system context ...
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... Three-state test and NAND tree test can be used to prevent the AMD-762 system controller from driving its pins and to verify con ivi AMD-762 sys con motherboard. The PLL bypass and clock output test modes are provided primarily for motherboard debug and can be used to verify system clocking and drive slower clocks into the system ...
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... NAND characterization of the device, and also reduces motherboard t est time. The AMD-762 syst em controller NAND trees are divided by I/O type, which create the following trees: n AMD Athlon system bus NAND tree This tree includes all signals on the AMD Athlon processor system bus ...
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... PCI NAND tree This tree includes PCICLK and PCI bus signals, excluding the RESET# input. The output of this tree is the GNT[2]# pin. The ordering for this NAND tree is shown in Table 5 on page 44. Chapter 3 Preliminary Information AMD-762™ System Controller Data Sheet Test 37 ...
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... AMD-762™ System Controller Data Sheet Table 2. AMD Athlon™ Processor System Bus NAND Tree Ordering Input Pin # Ball Name 1 P0_SADDOUT[14]# D-1 2 P0_SYSFILLVAL# J-8 3 P0_SADDOUT[10]# F-5 4 P0_SADDOUT[13]# E-2 5 P0_SADDOUT[07]# E-1 6 P0_SADDOUTCLK# E-3 7 P0_SADDOUT[05]# F-4 8 P0_SADDOUT[09]# F-2 9 P0_SADDOUT[12]# F-1 10 P0_SADDOUT[11]# G-5 11 P0_SADDOUT[08]# F-3 12 P0_SADDOUT[02]# G-1 13 P0_SADDOUT[03]# H-2 14 P0_SADDOUT[04]# G-3 15 P0_SADDOUT[06]# H-4 16 P0_SDATA[54]# H-6 17 P0_SDATA[55]# H-5 18 P0_SDATA[61]# H-7 19 P0_SDATA[50]# J-7 20 P0_SDATA[48]# K-7 21 P0_SDATAOUTCLK[3]# H-1 ...
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... AD-6 117 P1_SADDOUT[09]# AF-2 118 P1_SADDOUT[12]# AF-1 119 P1_SADDOUTCLK# AG-1 120 P1_SADDOUT[14]# AG-2 121 P1_SADDOUT[04]# AE-3 122 P1_SADDOUT[13]# AH-1 123 P1_SADDOUT[03]# AK-3 Chapter 3 Preliminary Information AMD-762™ System Controller Data Sheet Input Pin # Ball Name 124 P1_SADDOUT[02]# AJ-2 125 P1_SADDOUT[08]# AJ-3 126 P1_SADDOUT[06]# AF-3 127 P1_SADDOUT[05]# AG-3 128 P1_SDATA[54]# AL-4 129 P1_SDATA[61]# AE-5 130 P1_SDATA[48]# ...
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... AMD-762™ System Controller Data Sheet Table 2. AMD Athlon™ Processor System Bus NAND Tree Ordering (Continued) Input Pin # Ball Name 185 P1_SDATA[24]# AK-14 186 P1_SDATA[30]# AJ-12 187 P1_SDATA[28]# AJ-13 188 P1_SDATA[03]# AD-14 189 P1_SDATA[01]# AJ-14 190 P1_SDATA[07]# AE-13 191 P1_SDATA[00]# AE-14 192 P1_SDATA[05]# AL-14 193 P1_SDATA[09]# AD-15 194 P1_SCHECK[0]# ...
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... Table 3: AMD-762™ System Controller AGP NAND Tree Ordering Order Input Pin Name Ball 1 A_GNT# AD-27 2 SBA[1] AB-25 3 PIPE# AE-29 4 WBF# AC-26 5 SBA[5] AA-25 6 ST[1] AD-28 7 A_REQ# AD-29 8 ST[0] AC-27 9 ST[2] AC-28 10 SBA[7] AA-26 11 A_AD[30] Y-25 12 SBA[3] AB-27 13 RBF# AC-29 14 A_AD[28] Y-26 15 CBE[3]# V-25 16 SBA[2] AA-27 17 SBA[0] AB-29 18 A_AD[26] W-25 19 A_AD[20] U-25 20 A_AD[22] V-26 21 SBA[4] Y-27 22 SBSTB AA-28 Chapter 3 Preliminary Information AMD-762™ ...
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... AMD-762™ System Controller Data Sheet Table 4: AMD-762™ System Controller DDR NAND Tree Ordering Order Input Pin Name Ball 1 MDAT[59] E-29 2 MDAT[63] E-27 3 DQS[7] D-29 4 CLKOUT[5] F-26 5 DCSTOP# G-25 6 MDAT[58] E-28 7 MDAT[62] C-29 8 CLKOUT[2]# F-25 9 MDAT[57] C-27 10 DM[7] C-28 11 CLKOUT[2] E-26 12 CS[6]# D-25 13 MDAT[56] B-28 14 CLKOUT[5]# D-27 15 CS[5]# E-24 16 MDAT[60] B-27 17 CS[1]# E-23 18 MDAT[61] C-26 19 MDAT[51] A-27 20 MDAT[55] C-25 21 CS[7]# E-25 22 ...
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... Table 4: AMD-762™ System Controller DDR NAND Tree Ordering (Continued) Order Input Pin Name Ball 103 MAB[03] E-9 104 MDAT[28] C-7 105 MDAT[24] A-6 106 MAA[04] D-7 107 MDAT[22] A-5 108 MAB[04] E-8 109 MDAT[23] C-6 110 MDAT[19] B-6 111 MDAT[18] A-4 112 MAB[06] D-6 113 DM[2] B-4 114 MAA[06] ...
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... ovi Northbridge core logic directly from an external source without for PLLs AMD-762 syste m controller. This test mode is sometimes useful for motherboard debug and is required in the three-state and NAND tree test modes ...
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... PLL bypass mode as listed in Ta ble 6 below. Because the AMD-762 system controller internal logic normally uses clocks the SYSCLK 2x/ AGPCLK input, the PLL bypass mode requires that either clocks be driven in this mode, but they can be driven lowe r fre for rposes ...
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... AMD-762™ System Controller Data Sheet Table 7. Clock Output Test Mode Options AD[07:05] SYSCLK PLL Output GNT[5]# Pin 000 1x SYSCLK clock after internal divide by two 001 SYSCLK input 010 Reserved, undefined 011 Reserved, undefined 100 1x SYSCLK output from SYSCLK PLL 101 Reserved, undefined ...
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... Electrical Data 4.1 Absolute Ratings The AMD-762™ system controller is not designed to operate beyond the parameters shown in Table 8. Note: The absolute ratings in Table 8 and associated conditions Table 8. VDD_CORE, A_VDD, K7_VCORE VDD_AGP, VDD_PCI REF_5V V PIN V PIN System Bus V PIN V PIN ...
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... Operating Ranges Th e AMD-762 syst e m con t r oller rovi parameters are within the limits defined in Table 9. ...
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... DC Characteristics Table 11 shows the DC characteristics for the AMD-762 system controller. Table 12 on page 50 shows DC characteristics for the PCI I/Os. Table 13 on page 51 shows DC characteristics for AGP I/ mode. Table 14 on page 52 shows DC characteristics for AGP I/ and 4x modes. Table 10. ...
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... AMD-762™ System Controller Data Sheet 4.3.1 Voltage Sequencing Requirements The preferred sequence of volt ages AMD-762 system controller is from highest (5 VDC on the REF_5V pin) to the lowest. To accommodate the Suspend to RAM feat ure expected that the AMD-762 system controller’s 2.5-VDC core ...
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... PGA packaging. Generally, this means that com- ponents for expansion boards need to use alternatives to ceramic PGA packaging— that is, PQFP, BGA, etc. Chapter 4 Preliminary Information AMD-762™ System Controller Data Sheet Condition Min 0.5 V DDQ — ...
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... AMD-762™ System Controller Data Sheet Table 14. AGP 2x and 4x Mode DC Specifications* DC Specifications for 2x Mode Only at 3.3-Volt Signalling Symbol Parameter Description V Input Reference Voltage REF I V Pin Input Current REF REF C Input Pin Capacitance IN C Strobe to Data Pin Capacitance Delta IN DC Specifications for Mode at 1.5-Volt Signalling ...
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... Clock Switching Requirements Table 16 contains the switching characteristics of the SYSCLK input to the AMD-762 system controller for 100-MHz processor bus operation. These timings are all measured with respect to the volt age levels indicated by Figure 12 on page 54. Clock skew requirements are shown in Figure 14 on page 56. Table 17 on page 55 conta ins the switch ing istics of the AGPCLK inp u t for 66-MHz PCI bus operation ...
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... This parameter consid e red as one of the elements of clock skew between the AMD-762 system controller and the system logic. Table 16. SYSCLK Switching Requirements Symbol ...
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... PCICLK Rise Time PCICLK Period Stability * This table contains preliminary information, which is subject to change. 0.5 VDD_PCI 0.4 VDD_PCI 0.3 VDD_PCI Figure 13. AGPCLK and PCICLK Waveform Chapter 4 Preliminary Information AMD-762™ System Controller Data Sheet Preliminary Data Min Max 66 MHz 6.0 ns 6 –500 ps ...
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... DDR Interface Timing and Ta ble 20 show DDR SDRAM inte timings. Figure 15 on page 57 shows DDR clock specifications. The AMD-762 system controller’s DDR DRAM interface complies to JEDEC specifications for 100/133-MHz device timing. Table 19. DDR Clock Switching Characteristics for 100-MHz DDR Operation ...
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... CLKOUTH[5:0] CLKOUTL[5:0]# Figure 15. DDR Clock Specifications Table 21 shows the AMD-762 syst em controller preliminary timing information. Table 21. AMD-762™ System Controller Preliminary DDR Timing Information* Symbol Parameter Description V (AC) AC Input Low Voltage IL V (AC) AC Input High Voltage IH t ADDR/CMD Setup to CK ...
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... PLL unbuf_CCLK2X unbuf_CCLK Figure 16. AMD-762™ System Controller DDR Interface Outputs Conceptual Block Diagram early_CCLK set clr CCLK2X Clock Buffers set D Q Clock Buffers Q clr set clr set clr Memory Controller Logic set clr CK CK/ ADDR/CMD DQS ...
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DQSdly t ADhld t ADsu CK ADDR/CMD t WPREhld t WPREsu DQS DQ/DM t DQsu Timing parameter symbols defined at controller interface, not at memory device interface. Note: Figure 17. Address/Command and Memory Write Cycle Timing ...
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... Note: All information shown under From Chip I/O Buffers DQ DQS PDL Figure 18. AMD-762™ System Controller DDR Interface Inputs Conceptual Block Diagram 60 Preliminary Information preliminary. Figure 18 shows a block diagram of the AMD-762 system controller DDR interface inputs, and Figure 19 on page 61 shows memory read cycle timing. CCLK ...
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DQS DQ t CKhi CK Read ADDR/CMD DQS DQ Timing parameter symbols defined at controller interface, not at memory device interface (CAS latency = 2 shown unregistered). Note: Figure 19. Memory Read Cycle Timing t (max) QHrd t (min) DQSQrd ...
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... Data Out Figure 20. Setup, Hold, and Valid Delay Timings AGP Interface Timing The 4x AGP interface of the AMD-762 system controller can operate in three modes —1x, 2x, and 4x, and complies to the AGP specification parameters. The timings for the 1x mode, shown in Table 22 on page 63, are relative to AGPCLK ...
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... Turn-on Delay (Float to Active) on Note: * This table contains preliminary information, which is subject to change. 1. These signals are specified with a 10-pF load. Chapter 4 Preliminary Information AMD-762™ System Controller Data Sheet Preliminary Data Min Max Input Signal Requirements 5 Output Signal Characteristics ...
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... AMD-762™ System Controller Data Sheet Table 23. AGP 2x Mode Timings* Symbol Parameter Description t Receive Strobe Setup Time to AGPCLK RSsu t Receive Strobe Hold Time from AGPCLK RSH t Data Setup Time Relative to Strobe Dsu t Data Hold Time Relative to Strobe Dh t AGPCLK to Transmit Strobe Falling ...
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... These specifications refer to the setup and hold times for the strobe set started in the previous cycle. AGPCLK AD Strobe Figure 21. AGP 2x Strobe/ Data Turnaround Timings Chapter 4 Preliminary Information AMD-762™ System Controller Data Sheet Preliminary Data Min Max Transmitter Output Signals 1 – ...
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... AMD-762™ System Controller Data Sheet AGPCLK AMD-762™ Transmit Data AMD-762 Transmit Strobe AMD-762 Receive Data AMD-762 Receive Strobe Figure 22. AGP 2x Timing Diagram AGPCLK Transmit Strb/Strb# t DVb Transmit Data t DVa Receive Strb/Strb# t DSu Receive Data Figure 23. AGP 4x Timing Diagram 66 Preliminary Information ...
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... AGP 4x Strobe/ Data Turnaround Timing PCI Interface Timings Table 25 on page 68 shows the PCI interface timings. Table 26 shows 66-MHz PCI interface timings. All of the timings are relative to PCLK. Chapter 4 Preliminary Information AMD-762™ System Controller Data Sheet t OFFD t OFFS Electrical Data t ...
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... AMD-762™ System Controller Data Sheet Table 25. 33-MHz PCI Interface Timings* Symbol Parameter Description AD[63:0] Setup Time SBREQ#, REQ[6:0]# Setup Time Setup Time for FRAME# STOP TRDY# DEVSEL# IRDY# C/BE[3:0]# WSC# REQ64# ACK64# AD[63:0] Hold Time Hold Time for FRAME# STOP# TRDY# DEVSEL# ...
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... Min Max RESET WSC clks , and 50 pF for t min max. Electrical Data AMD-762™ System Controller Data Sheet Figure Notes ...
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... AMD-762™ System Controller Data Sheet 4.5 Athlon™ Processor System Bus Timings Table 27 shows the AMD Athlon processor system bus timings. Table 27. AMD Athlon™ Processor System Bus/AMD-762™ System Controller AC Specification Group Symbol Parameter Description T Output skew with respect to ...
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... Package Specifications Figure 25 on page 72 shows the package specifications for the AMD-762™ system controller. Chapter 5 Preliminary Information AMD-762™ System Controller Data Sheet Package Specifications 71 ...
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... AMD-762™ System Controller Data Sheet AMD PACKAGE SYMBOL MIN. MAX. D/E 39.80 40.20 D1/E1 38.10 BSC. --- D2/E2 D3/E3 21.79 A 4.869 5.257 A1 1.688 A2 1.322 b 0.79 e 1.27 BSC COLUMNS 0.15 aaa bbb 0.26 ccc 0.005 Figure 25. 949-Pin Ceramic Column Grid Array (CCGA) Package 72 Preliminary Information NOTES: 1. ALL DIMENSIONS ARE SPECIFIED IN MILLIMETER. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M-1994. ...
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... Pin Designations cludes conn ecti on diagra m and pin designation tables with pins grouped by function. Chapter 6 Preliminary Information AMD-762™ System Controller Data Sheet Pin Designations 73 ...
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... AMD-762™ System Controller Data Sheet NC1 MDAT1 DQS0 B NC28 MDAT5 VDD_CORE DM0 C NC30 NC31 MDAT4 MDAT0 MDAT6 D P0_SADDOUT14# P0_K7_VCORE0 PDL_OUTPUT_TES T DDR_REF VSS E P0_SADDOUT7# P0_SADDOUT13# P0_SADDOUTCLK# VSS NC36 F P0_SADDOUT12# P0_SADDOUT9# P0_SADDOUT8# P0_SADDOUT5# P0_SADDOUT10# G P0_SADDOUT2# P0_K7_VCORE1 P0_SADDOUT4# VSS P0_SADDOUT11# P0_K7_VCORE7 ...
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... VSS AGPCLK AK P1_SADDIN11# P1_SADDIN10# P1_K7_VCORE7 DEBUG0# ROM_SCK AL P1_SADDIN5# P1_SADDIN4# P1_CLKFWDRST P1_S YSFILLVALID# ROM_SDA Chapter 6 Preliminary Information AMD-762™ System Controller Data Sheet DM5 MDAT46 MDAT52 MDAT54 MDAT55 MDAT60 VDD_CORE MDAT43 MDAT49 VDD_CORE MDAT50 MDAT57 DQS5 MDAT47 ...
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... AMD-762™ System Controller Data Sheet Table 28. AMD-762™ System Controller Pin Functional Grouping ( DDR DRAM Name No. Name No. MAA[14] G-18 CS[0]# H-21 MAA[13] G-19 RASB# F-20 MAA[12] F-9 RASA# G-20 MAA[11] H-11 CASB# G-21 MAA[10] F-18 CASA# G-22 MAA[09] G-10 WEB# H-20 MAA[08] G-11 WEA# E-21 MAA[07] G-9 CKEB F-8 MAA[06] G-12 CKEA G-8 MAA[05] E-11 DQS[8] C-16 MAA[04] F-14 DQS[7] C-28 MAA[03] ...
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... Table 29. AMD-762™ System Controller Pin Functional Grouping ( PCI Bus Name No. Name No. AD[63] R-24 AD[17] W-29 AD[62] N-27 AD[16] V-27 AD[61] N-25 AD[15] U-27 AD[60] M-27 AD[14] U-26 AD[59] M-29 AD[13] T-31 AD[58] M-26 AD[12] R-30 AD[57] P-24 AD[11] T-27 AD[56] L-31 AD[10] V-24 AD[55] M-25 AD[09] R-31 AD[54] L-30 AD[08] T-29 AD[53] M-28 AD[07] U-25 AD[52] K-31 AD[06] R-26 AD[51] L-29 AD[05] U-24 AD[50] L-27 AD[04] P-31 AD[49] L-28 AD[03] T-25 AD[48] L-26 AD[02] P-30 AD[47] K-29 AD[01] R-29 AD[46] K-27 AD[00] P-27 AD[45] M-24 CBE[7]# N-31 AD[44] J-27 CBE[6]# N-29 AD[43] L-25 CBE[5]# M-31 AD[42] J-31 CBE[4]# R-25 AD[41] J-29 CBE[3]# Y-24 AD[40] J-30 CBE[2]# W-25 AD[39] J-28 CBE[1]# V-25 AD[38] H-31 CBE[0]# R-27 AD[37] J-26 PCICLK AH-21 AD[36] H-30 DEVSEL# V-28 AD[35] L-24 FRAME# V-31 AD[34] G-31 WSC# H-28 AD[33] K-25 IRDY# V-29 AD[32] F-31 PAR U-31 AD[31] AA-27 PAR64 M-30 AD[30] Y-26 SERR# U-29 AD[29] Y-27 STOP# U-30 AD[28] AA-30 TRDY# V-30 AD[27] Y-30 REQ64# P-26 AD[26] AA-31 ACK64# R-28 AD[25] AA-28 M66EN U-28 AD[24] Y-31 REQ[0]# E-30 AD[23] Y-25 REQ[1]# F-30 AD[22] W-27 REQ[2]# H-25 AD[21] Y-29 REQ[3]# ...
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... AMD-762™ System Controller Data Sheet Table 30. AMD-762™ System Controller Pin Functional Grouping ( Connects Name No. Name NC0 A-29 P0_CLKFWDRST NC1 A-3 P0_CONNECT NC2 AH-23 P0_PROCRDY NC4 AA-29 P0_SYSCLK NC6 AA-8 P0_SADDIN[02]# NC8 AC-8 P0_SADDIN[03]# NC9 AD-18 P0_SADDIN[04]# NC10 AD-21 P0_SADDIN[05]# NC11 AC-7 P0_SADDIN[06]# NC12 AD-9 P0_SADDIN[07]# NC13 AE-20 P0_SADDIN[08]# ...
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... Table 31. AMD-762™ System Controller Pin Functional Grouping ( Processor 1 AMD Athlon™ System Bus Name No. Name P1_CLKFWDRST AL-19 P1_SDATA[07]# P1_CONNECT AJ-19 P1_SDATA[08]# P1_PROCRDY AE-19 P1_SDATA[09]# P1_SADDIN[02]# AG-17 P1_SDATA[10]# P1_SADDIN[03]# AH-18 P1_SDATA[11]# P1_SADDIN[04]# AL-18 P1_SDATA[12]# P1_SADDIN[05]# AL-17 P1_SDATA[13]# P1_SADDIN[06]# AF-17 P1_SDATA[14]# P1_SADDIN[07]# AG-16 P1_SDATA[15]# P1_SADDIN[08]# AG-18 P1_SDATA[16]# P1_SADDIN[09]# ...
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... AMD-762™ System Controller Data Sheet Table 32. AMD-762™ System Controller Pin Functional Grouping ( VDD Name No. Name No. VDD_CORE AA-11 VDD_CORE M-22 VDD_CORE AA-13 VDD_CORE N-11 VDD_CORE AA-15 VDD_CORE N-13 VDD_CORE AA-17 VDD_CORE N-15 VDD_CORE AA-19 VDD_CORE N-17 VDD_CORE B-10 VDD_CORE N-19 VDD_CORE B-13 VDD_CORE N-21 VDD_CORE B-16 VDD_CORE P-12 VDD_CORE B-19 VDD_CORE P-14 VDD_CORE B-22 VDD_CORE P-16 VDD_CORE B-25 VDD_CORE P-18 VDD_CORE ...
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... Signal Descriptions Table 34 on page 82 contains a description of the AMD-762™ system controller signals. Table 33 describes the t e rms used in the signal descript ion table. The signals are organized within the following functional groups: • • • • • ...
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... SADDIN[14:2]# channel on each edge of SADDINCLK#. AMD Athlon Processor System Bus Connect System Address In Clock SADDINCLK# is the single-ended source-synchronous clock for the SADDIN[14:2]# bus, driven by the AMD-762 system controller. Each clock edge is used to transfer probe and SADDINCLK# O data movement commands to the processor. ...
Page 95
... SDATAOUTCLK[3:0]#. SCHECK[7:0]# are floated by RESET#. Check bits for write data are driven by the processor and check bits for read data are driven by the system controller. The AMD-762 system controller drives the previous data value between transfers to prevent floating inputs. AMD Athlon Processor System Bus Processor Data Channel The SDATA[63:0]# transfer data between the processor and system ...
Page 96
... The FRAME# pin is asserted by the AMD-762 system controller to indicate the beginning FRAME# STS of a bus transaction. FRAME# is sampled by the AMD-762 PCI target controller when an external bus master is performing a transaction on the PCI bus. PCI Bus Grant As the PCI bus arbiter, the AMD-762 system controller asserts one of these device-specific bus grant signals off the rising clock edge to indicate to an initiator that it has been granted control of the PCI bus the next time the bus is idle ...
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... Type PCI Initiator Ready The AMD-762™ system controller asserts this signal during PCI transactions to indicate B that write data is valid ready to receive read data sampled by the AMD-762 IRDY# system controller during memory transactions by external bus masters to DRAM. STS This pin is also optionally used in test modes as described in Table 36 on page 98, and in Chapter 3 ...
Page 98
... AGP A_SERR# pin assertion errors to error reporting logic on the AMD-766 peripheral bus controller. PCI Stop target, the STOP# signal is asserted by the AMD-762 PCI target logic to initiate a STOP# STS target disconnect, ending the current transfer master, the AMD-762 system controller ends the current transfer when it samples the STOP# signal asserted ...
Page 99
... TS The AMD-768™ peripheral bus controller or AMD-766™ peripheral bus controller requests that the AMD-762™ system controller issue a fence command to its buffers by placing a single PCICLK pulse on WSC#. The AMD-762 system controller then marks the data currently in its buffers and waits for this data to reach processor-accessible (coherent) space ...
Page 100
... DRAMs. (The DM pins provide additional strobes when accessing a x4 DIMM.) During reads, the DDR DRAMs source the DQS strobes aligned with MDAT and are used within the AMD-762 system controller to capture read data. (The DM pins are used to receive the DQS signals from the DDR DRAMs when accessing a x4 DIMM.) MDAT[63:0] are floated when neither the AMD-762 system controller nor the memory are driving the bus ...
Page 101
... AGP/ APCI Clock AGPCLK I AGPCLK receives a 66-MHz clock from the system clock generator. AGPCLK is used by the AMD-762™ system controller logic in the AGP clock domain. Chapter 7 Preliminary Information AMD-762™ System Controller Data Sheet Description ...
Page 102
... B The AMD-762 system controller asserts this signal during APCI transactions to indicate that A_IRDY# STS write data is valid ready to receive read data sampled by the AMD-762 system controller during transactions by the AGP master. APCI Bus Parity B PAR is used to generate and check for even parity across the AAD[31:00] and A_C/BE[3:]# A_PAR pins ...
Page 103
... This signal indicates that the AGP master’s input buffer is full, and that it cannot accept RBF# I more read data. When this signal is asserted by the AGP master, the AMD-762 system controller does not attempt to return previously requested low-priority read data. AGP Write Buffer Full ...
Page 104
... Type AGP Status This bus is used to provide status from the AMD-762™ system controller to the AGP master. These signals are valid only when the A_GNT# signal is asserted (Low) and must be ignored by the AGP master at all other times. The status bits are encoded as follow: 000 = Indicates that previously requested low-priority read or flush data is being returned to the master ...
Page 105
... SIP parameters are required that are different than those supplied by the AMD-762™ system controller. This pin must be pulled Low when using the internal SIP ROM table on the AMD-762 system controller or pulled High to use the external ROM. ...
Page 106
... Initialization Pinstrapping The AMD-762 system controller requires various pinstrapping options to define the SIP stream returned to the AMD Athlon processor aft er reset , as well as to define specific AMD-762 system controller operating parameters. The pinstraps are set by 10K pullup or pulldown resistors attached externally to PCI bus pins, and they are sampled during reset ...
Page 107
... Chapter 3 for details of this test mode bit. The value of this pinstrap can be read in the Configuration Status register (Dev 0:F0:0x88). Inclk_Delay_Enable When this pin is pulled High, forwarded clocks originating in the AMD-762™ system controller are delayed 1/4 SysClk period to place their edge in the nominal center of the AD[24] I associated data ...
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... AMD-762™ System Controller Data Sheet Table 35. Initialization Pinstrapping (Continued) Signal Type 66-MHz PCI Mode This bit is used to specify that the desired PCI clock speed is 66 MHz. This pin should be pulled up if the motherboard supports the 66/33-MHz PCI speed option as described in ...
Page 109
... PCI signal pullup resistors need replacing temporarily with pulldown resistors. This action should be done only for lab testing and not in a production environment. These signals include the following: Chapter 7 Preliminary Information AMD-762™ System Controller Data Sheet Description 11.0 0100 5.0 1000 11 ...
Page 110
... ACPI S1 and S3 power management states. Refer to “Power Management” on page 25 for details of the S1 and S3 modes AMD-762 configuration registers are initialized to a known value when RESET# is asserted ...
Page 111
... Parked signals maintain their previous value Park Z Park Park Z Park Z AMD-762™ system controller asserts per PCI 64-bit Park Z protocol. Park Active Z Can be disabled via configuration register. Active Z Can be disabled via configuration register. Active Z Can be disabled via configuration register ...
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... AMD-762™ System Controller Data Sheet Table 37. Reset Pin States (Continued) Pin Name RESET# State S1 State S3 State MDAT[63:0] Z MECC[7:0] Z CASA# 1 CASB# 1 CLKOUT[5:0] Active CLKOUT[5:0]# Active RASA# 1 RASB# 1 WEA# 1 WEB# 1 A_AD[31:00] Z A_C/BE[3:0]# Z A_DEVSEL# Z A_FRAME# Z A_GNT# 1 A_IRDY# Z A_PAR Z A_STOP# Z A_TRDY# Z ADSTB[1:0] Z ADSTB[1:0]# Z SBSTB ...
Page 113
... Valid combinations are configurations that are or will be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Ordering Information AMD-762™ System Controller Data Sheet Case Temperature 2.375 V–2.625 ° ...
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... AMD-762™ System Controller Data Sheet 102 Preliminary Information Ordering Information 24416C—December 2001 Chapter 8 ...
Page 115
... Conventions, Abbreviations, and References Preliminary Information first read the register A word is two bytes (16 bits) A doubleword is four bytes (32 bits) A quadword is eight bytes (64 bits) An AMD Athlon™ processor quadwords (64 bytes) AMD-762™ System Controller Data Sheet and change only the cache line is eight 103 ...
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... AMD-762™ System Controller Data Sheet n Addressing—Memory is addressed as a series of bytes on eight-byte (64-bit) boundaries in which each byte can be separately enabled. n Abbreviations—The following notation is used for bits and bytes: • • • See Table 40 for more abbreviations. n Little-Endian Convention —The byte with the address xx ...
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... Meaning h Hexadecimal K Kilo- Kilobyte M Mega- Mbit Megabit Megabyte MHz Megahertz m Milli- ms Millisecond mW Milliwatt Micro- A Microampere F Microfarad H Microhenry s Microsecond V Microvolt n nano- nA nanoampere nF nanofarad nH nanohenry ns nanosecond ohm Ohm p pico- pA picoampere pF picofarad pH picohenry ps picosecond s Second V Volt W Watt AMD-762™ System Controller Data Sheet 105 ...
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... AMD-762™ System Controller Data Sheet Table 40 contains the definitions of acronyms used in this document. Table 40. Abbreviation CCGA DIMM DRAM EPROM GART HSTL JEDEC 106 Preliminary Information Acronyms Meaning AAT AGP Address Translator ACK Acknowledge ACPI Advanced Configuration and Power Interface AGP ...
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... Physical Page Address PT Page Tables PTE Page Table Entries RAM Random Access Memory ROM Read Only Memory SBA Sideband Address Synchronous Direct Random Access Memory SIP Serial Initialization Packet System Management Bus SMC SDRAM Memory Controller AMD-762™ System Controller Data Sheet 107 ...
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... AMD-762™ System Controller Data Sheet Table 40. Abbreviation SRAM SROM 108 Preliminary Information Acronyms (Continued) Meaning SPD Serial Presence Detect Synchronous Random Access Memory Serial Read Only Memory TLB Translation Lookaside Buffer TOM Top of Memory TTL Transistor Transistor Logic VAS Virtual Address Space ...
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... Patterson, Morgan Kaufman Publishers, San Mateo, CA, 1990. Websites Visit the AMD website for documentation of AMD products. Other websites of interest include the following: n JEDEC home page —www.jedec.org n IEEE home page —www.computer.org n AGP Forum—www.agpforum.org Conventions, Abbreviations, and References Preliminary Information AMD-762™ System Controller Data Sheet www.amd.com 109 ...
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... AMD-762™ System Controller Data Sheet 110 Preliminary Information Conventions, Abbreviations, and References 24416C—December 2001 ...