DS42515 AMD, DS42515 Datasheet

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DS42515

Manufacturer Part Number
DS42515
Description
MCP Flash Memory and SRAM
Manufacturer
AMD
Datasheet
DS42515
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL164D Bottom Boot 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
Flash Memory Features
ARCHITECTURAL ADVANTAGES
PERFORMANCE CHARACTERISTICS
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Power supply voltage of 2.7 to 3.3 volt
High performance
— 85 ns maximum access time
Package
— 69-Ball FBGA
Operating Temperature
— –25°C to +85°C
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
— Zero latency between read and write operations
Secured Silicon (SecSi) Sector: Extra 64 KByte sector
— Factory locked and identifiable: 16 bytes available for
— Customer lockable: Can be read, programmed, or erased
Zero Power Operation
— Sophisticated power management circuits reduce power
Bottom boot block
Manufactured on 0.23 µm process technology
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
High performance
— 85 ns access time
— Program time: 7 µs/word typical utilizing Accelerate function
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125 C
— Reliable operation for the life of the system
executing erase/program functions in other bank
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
just like other sectors. Once locked, data cannot be changed
consumed during inactive periods to nearly zero
flash standard
Refer to AMD’s Website (www.amd.com) for the latest information.
SOFTWARE FEATURES
HARDWARE FEATURES
SRAM Features
Data Management Software (DMS)
— AMD-supplied software manages data programming and
— Eases sector erase limitations
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in same
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
Any combination of sectors can be erased
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
WP#/ACC input pin
— Write protect (WP#) function allows protection of two outermost
— Acceleration (ACC) function accelerates program timing
Sector protection
— Hardware method of locking a sector, either in-system or
— Temporary Sector Unprotect allows changing data in
Power dissipation
— Operating: 50 mA maximum
— Standby: 7 µA maximum
CE1#s and CE2s Chip Select
Power down features using CE1#s and CE2s
Data retention supply voltage: 1.5 to 3.3 volt
Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)
erasing, enabling EEPROM emulation
bank
program or erase cycles
program command sequences
completion
reading array data
boot sectors, regardless of sector protect status
using programming equipment, to prevent any program or
erase operation within that sector
protected sectors in-system
Publication# 23784
Issue Date: March 15, 2001
Rev: B Amendment/1

Related parts for DS42515

DS42515 Summary of contents

Page 1

... DS42515 Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL164D Bottom Boot 16 Megabit ( 8-Bit 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features Power supply voltage of 2.7 to 3.3 volt High performance — ...

Page 2

... The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly re- duced in both modes. DS42515 ...

Page 3

... Unlock Bypass Command Sequence . . . . . . . . 23 Figure 3. Program Operation . . . . . . . . . . . . . . . 24 Chip Erase Command Sequence . . . . . . . . . . . . 24 Sector Erase Command Sequence . . . . . . . . . . . 24 Erase Suspend/Erase Resume Commands . . . . 25 Figure 4. Erase Operation . . . . . . . . . . . . . . . . . 25 Table 12. DS42515 Command Definitions . . . . 26 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 27 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 5. Data# Polling Algorithm . . . . . . . . . . . 27 RY/BY#: Ready/Busy DQ6: Toggle Bit Figure 6 ...

Page 4

... Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 56 FLA069—69-Ball Fine-Pitch Grid Array Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 57 Revision A (July 20, 2000 Revision B (March 7, 2001 Global . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Sector/Sector Block Protection/Unprotection . . 57 Common Flash Memory Interface (CFI Command Definitions . . . . . . . . . . . . . . . . . . . . 57 AC Characteristics—Alternate CE#f Controlled Erase and Program Operations . . . . . . . . . . . . 57 Revision B+1 (March 15, 2001 DS42515 ...

Page 5

... A–1 WP#/ACC RESET# CE#f CIOf A0 to A19 A0 to A17 SA LB#s UB#s WE# OE# CE1#s CE2s CIOs Flash Memory RY/BY# 16 Mbit Flash Memory DQ0 to DQ15/A– CCQ SS SSQ 4 Mbit DQ0 to DQ15/A–1 Static RAM DS42515 DS42515 SRAM DQ0 to DQ15/A–1 5 ...

Page 6

... FLASH MEMORY BLOCK DIAGRAM A0–A19 RY/BY# A0–A19 RESET# STATE CONTROL WE# & CE# COMMAND CIOf REGISTER WP#/ACC DQ0–DQ15 A0–A19 6 Upper Bank Address Upper Bank X-Decoder Status Control X-Decoder Lower Bank Lower Bank Address DS42515 OE# CIOf DQ0–DQ15 ...

Page 7

... Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150 C for prolonged periods of time. DS42515 Flash only A10 NC SRAM only Shared E10 NC F10 ...

Page 8

... The state machine outputs dictate the function of the device. Tables 1 through 3 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections de- scribe each of these operations in further detail. DS42515 DQ0–DQ15 RY/BY# ...

Page 9

... 8.5–12 9.0 ± 0 Don’t Care Sector Address and CE2s = V at the same time. IH the boot sectors protection will be removed. IH DS42515 ; SRAM Word Mode, CIOs = WP#/ACC DQ0– DQ7 DQ8–DQ15 (Note OUT OUT ...

Page 10

... 8.5–12 9.0 ± 0 Don’t Care Sector Address and CE2s = V at the same time. IH the boot sectors protection will be removed. IH DS42515 ; SRAM Byte Mode, CIOs = WP#/ACC RESET# DQ0–DQ7 DQ8–DQ15 (Note OUT H ...

Page 11

... 8.5–12 9.0 ± 0 Don’t Care Sector Address and CE2s = V at the same time. IH the boot sectors protection will be removed. IH DS42515 ; SRAM Byte Mode, CIOs = WP#/ACC RESET# DQ0–DQ7 DQ8–DQ15 (Note 4) H L/H D High-Z OUT H ...

Page 12

... Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 represent the current specifications for read-while-pro- gram and read-while-erase, respectively. DS42515 on this pin, the device auto- HH for operations other than accelerated pro- and I in the DC Characteristics table ...

Page 13

... The output pins are placed in the high impedance state. Table 4. Device Bank Division Bank 1 Sector Sizes Megabits Eight 8 Kbyte/4 Kword, 8 Mbit fifteen 64 Kbyte/32 Kword DS42515 ± 0.3 V, the de RESET# is CC4 ± 0.3 V, the standby cur- SS (during Embedded Algorithms). The (not during Embed- ...

Page 14

... A19:A0 in word mode (CIOf=V IL SecSi Sector Addresses for Bottom Boot Devices Sector Address Sector A19–A12 Size 00000XXX 64/32 DS42515 (x8) (x16) Address Range 00000h–00FFFh 01000h–01FFFh 02000h–02FFFh 03000h–03FFFh 04000h–04FFFh 05000h–05FFFh 06000h–06FFFh 07000h–07FFFh 08000h– ...

Page 15

... Table 7). This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- DS42515 the WP#/ACC pin, the de the WP#/ACC pin, the de- ...

Page 16

... Perform Erase or Program Operations RESET Temporary Sector Unprotect Completed Notes: 1. All protected sectors unprotected (If WP#/ACC = V outermost boot sectors will remain protected). 2. All previously protected sectors are protected once again. Figure 1. Temporary Sector Unprotect Operation DS42515 START ID (Note 1) IH (Note ...

Page 17

... Reset PLSCNT = 1 Increment PLSCNT No Yes PLSCNT = 1000? Yes Device failed Sector Unprotect Algorithm DS42515 START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes No All sectors protected? Yes ...

Page 18

... Noise pulses of less than 5 ns (typical) on OE#, CE#f or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one CE#f and WE# must be a logical zero while OE logical one. DS42515 This IH ID power- the device does not ac greater than V . ...

Page 19

... Query Unique ASCII string “QRY” 0059h 0002h Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h DS42515 Description 19 ...

Page 20

... Erase Block Region 2 Information 0000h 0001h 0000h 0000h Erase Block Region 3 Information 0000h 0000h 0000h 0000h Erase Block Region 4 Information 0000h 0000h DS42515 Description pin present) PP pin present µs N µ s (00h = not supported (00h = not supported) ...

Page 21

... Not Supported Word Page Word Page ACC (Acceleration) Supply Minimum 0085h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 0095h 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 000Xh 02h = Bottom Boot Device, 03h = Top Boot Device DS42515 Description 21 ...

Page 22

... A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h unprotected. (Refer to Ta- bles 5–6 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend). DS42515 ...

Page 23

... Figure 3 illustrates the algorithm for the program oper- ati on . Ref Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams. DS42515 any operation HH 23 ...

Page 24

... When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- termine the status of the erase operation by reading DS42515 ...

Page 25

... Write Erase Command Sequence (Notes 1, 2) Data Poll to Erasing Bank from System No Data = FFh? Yes Erasure Completed Notes: 1. See Table 12 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer. Figure 4. Erase Operation DS42515 Embedded Erase algorithm in progress 25 ...

Page 26

... Table 12. DS42515 Command Definitions Command Sequence (Note 1) Addr Read (Note 6) 1 Reset (Note 7) 1 XXX Word 555 Manufacturer ID 4 Byte AAA Word 555 Device ID 4 Byte AAA Word 555 SecSi Sector Factory 4 Protect (Note 9) Byte AAA Word 555 Sector Protect Verify ...

Page 27

... During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm DS42515 Yes Yes PASS 27 ...

Page 28

... Note: The system should recheck the toggle bit even if DQ5 = “1” because the toggle bit may stop toggling as DQ5 changes to “1.” See the subsections on DQ6 and DQ2 for more information. Figure 6. Toggle Bit Algorithm DS42515 No No Program/Erase Operation Complete ...

Page 29

... DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 13 shows the status of DQ3 relative to the other status bits. DS42515 29 ...

Page 30

... The device outputs array data if the system addresses a non-busy bank. 30 Table 13. Write Operation Status DQ7 DQ5 DQ6 (Note 2) (Note 1) DQ7# Toggle 0 Toggle 1 No toggle Data Data Data DQ7# Toggle DS42515 DQ2 DQ3 RY/BY# (Note 2) 0 N/A No toggle Toggle 0 0 N/A Toggle 1 Data Data ...

Page 31

... V f/V s for standard voltage range . . 2 3 Operating ranges define those limits between which the func- tionality of the device is guaranteed –2 +2 +0.5 V 2.0 V Figure 8. Maximum Positive DS42515 ) . . . . . . . . .–25°C to +85° Overshoot Waveform 31 ...

Page 32

... CE1 MHz IL CE2s = MHz CE1#s = 0.2 V, CE2s = V s – 0.2V 1 MHz CC 1) CE1 CE2s = CE2s = V IL CE1 – 0.2V, CE2s – 0.2V CC CE2s 0.2V –0.2 2.4 DS42515 Typ Max Unit 1.0 µA 35 µA 1.0 µA 35 µ 0.2 5 µA 0.2 5 µ ...

Page 33

... OH CE1 CE2 = V , Other IH IL inputs = CE1#s V – 0.2 V, CE2 V – 0.2 V (CE1#s controlled) or CE2 0.2 V (CE2s controlled), CIOs = Other input = DS42515 Min Typ Max Unit 8.5 9.5 V 8.5 12.5 V 0. –0.4 CC 2.3 2 ns. Typical sleep mode current is ...

Page 34

... Note: Addresses are switching at 1 MHz Figure 9. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 Note 1500 2000 2500 Time Frequency in MHz Figure 10. Typical I vs. Frequency CC1 DS42515 3000 3500 4000 3 ...

Page 35

... Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels INPUTS Steady Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Measurement Level DS42515 85 ns Unit 1 TTL gate 0.0–3 ...

Page 36

... AC CHARACTERISTICS SRAM CE#s Timing Parameter JEDEC Std Description — t CE#s Recover Time CCR E#f E1#s E2s Figure 13. Timing Diagram for Alternating Between SRAM to Flash 36 Test Setup — CCR CCR t t CCR CCR DS42515 Speed Unit 85 Min 0 ns ...

Page 37

... V Test Setup CE# Read Toggle and Data# Polling t RC Addresses Stable t ACC OEH t CE HIGH Z Figure 14. Read Operation Timings DS42515 85 ns Speed Min Max HIGH Z Output Valid Unit ns ns ...

Page 38

... Note: Not 100% tested. RY/BY# CE#f, OE# RESET# RY/BY# CE#f, OE# RESET# 38 Description Max Max Min Min Min Min Ready Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms t Ready t RP Figure 15. Reset Timings DS42515 85 ns Unit 20 s 500 ns 500 ...

Page 39

... Output t FLQZ t ELFH Data Output Data Output (DQ0–DQ7) (DQ0–DQ14) Address DQ15 Input Output t FHQV The falling edge of the last WE# signal t SET ( HOLD AH and t specifications DS42515 Typ Max Unit Data Output (DQ0–DQ7) Address Input 39 ...

Page 40

... Program/Erase Valid to RY/BY# Delay BUSY Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. 40 CE#f low during toggle bit Read Toggle and Data# Polling Byte Word DS42515 85 ns Speed Unit Min Typ Max ...

Page 41

... Figure 19. Accelerated Program Timing Diagram WPH A0h t BUSY is the true data at the program address. OUT Figure 18. Program Operation Timings DS42515 Read Status Data (last two cycles WHWH1 D Status OUT VHH 41 ...

Page 42

... SA = sector address (for Sector Erase Valid Address for reading status data (see “Write Operation Status”). . These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings 555h for chip erase WPH t DH 30h 10 for Chip Erase t BUSY DS42515 Read Status Data WHWH2 In Complete Progress t RB ...

Page 43

... OEH GHWL Valid Out t SR/W Read Cycle Complement Complement Status Data Status Data DS42515 Valid PA Valid PA t CPH t CP Valid Valid In In CE#f Controlled Write Cycles VA High Z Valid Data True High Z True Valid Data 43 ...

Page 44

... DQ2 and DQ6 AHT AS t AHT t ASO t CEPH t OEPH t OE Valid Valid Status Status (second read) Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program Figure 24. DQ2 vs. DQ6 DS42515 Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read ...

Page 45

... Note: Not 100% tested RESET VIDR CE#f WE# RY/BY# Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram Min Min Min Min Program or Erase Command Sequence t RSP DS42515 85 ns Speed Unit 500 ns 250 VIDR t RRB ...

Page 46

... Data 60h 1 µs CE#f WE# OE# * For sector protect For sector unprotect Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram 46 Valid* Valid* Verify 60h 40h Sector/Sector Block Protect: 150 µs, Sector/Sector Block Unprotect DS42515 Valid* Status ...

Page 47

... Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information Speed Min Typ Byte 5 Word 7 4 0.7 DS42515 Max Unit µs µs sec 47 ...

Page 48

... SA for sector erase 555 for chip erase Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT DS42515 PA DQ7# D OUT ...

Page 49

... OHZ t Output Data Hold from Address Change OH ddress ata Out Previous Data Valid Note: CE1 CE2s = WE Figure 28. SRAM Read Cycle—Address Controlled UB#s and/or LB DS42515 Min Max Unit ...

Page 50

... At any given temperature and voltage condition, t interconnection CO1 t CO2 OLZ t BLZ t LZ Data Valid Figure 29. SRAM Read Cycle (Max.) is less than t (Min.) both for a given device and from device to device HZ LZ DS42515 BHZ t OHZ ...

Page 51

... (See Note (See Note 3) High applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when DS42515 Min Max Unit ...

Page 52

... (See Note 5) High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when DS42515 t (See Note Data Valid High-Z is measured from the beginning of write ...

Page 53

... Note 4) WP (See Note High-Z applied in case a write ends as CE1#s or WE# going high low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when DS42515 t (See Note Data Valid High-Z is measured from the beginning of write ...

Page 54

... V, one pin at a time. CC Test Setup OUT Test Conditions DS42515 Unit Comments sec Excludes 00h programming prior to erasure (Note 4) sec µs µs Excludes system level µs overhead (Note 5) sec , 1,000,000 cycles. Additionally, CC Min Max – ...

Page 55

... 1.5 V, CE1 (See Note) See data retention waveforms – 0.2 V (CE1#s controlled) or CE2s 0.2 V (CE2s controlled), CIOs = V Data Retention Mode t SDR CE1 0 Data Retention Mode t SDR CE2s £ 0.2 V DS42515 Min Typ Max Unit 1.5 3.3 – 0 RDR t RDR V µ ...

Page 56

... PHYSICAL DIMENSIONS FLA069—69-Ball Fine-Pitch Grid Array 0.15 C (2x) 8.00 BSC B 0.97 1.40 (max) 1.07 0.20 (min) 0.40 7.20 BSC 0.80 56 11.00 BSC Pin A1 DATUM A Corner Index Mark 7.20 BSC 0.80 0. 0.25 (69x) 0.35 0. 0.08 DS42515 A DATUM B 0.15 C (2x ...

Page 57

... Accelerated Programming Operation: Cor- WHWH1 rected typical value of 7 µ µs. Revision B+1 (March 15, 2001) Added “Am29DL164D Bottom Boot” to the product de- scription on the top portion of the first page. DS42515 57 ...

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