AMD-766AC AMD [Advanced Micro Devices], AMD-766AC Datasheet - Page 16

• Manufacturer Part Number: AMD-766AC
• Description: Peripheral Bus Controller
• Manufacturer: AMD [Advanced Micro Devices]

23167B – March 2001
4.2 PCI Interface
The IC connects to the host through a 32-bit, 33 MHz PCI interface.
4.2.1
PCI target accesses to the IC are acknowledged with DEVSEL# using either PCI-defined medium or subtractive
decoding. The following equation specifies the timing based on the address space and configuration. See section
10.3 for a description of the logic convention.
START_OF_DEVSEL = (PCI_COMMAND != SPECIAL_CYCLE) &
Where the following are defined:
CMD2:
CONFIG_SPACE[4:0]:
FRAME1:
FRAME3:
IDE_HIT
ISA_HIT
DMAC_HIT
PCI_COMMAND:
USB_HIT
BIOS_ADDR_SPACE:
4.3
4.3.1
The IC’s ISA interface includes a 24-bit address bus and an 8-bit data bus. Only target cycles to the ISA bus are
supported; master and DMA cycles are not supported. Memory and IO accesses are supported. Target transactions
to the IC may be routed to the ISA bus if ISABIOS specifies that the BIOS address space specified by C0A43 is on
the ISA bus or if C0A48[SUB] specifies that the ISA bus is the default path for unclaimed transactions.
Default path memory accesses to greater than the 16-megabyte address space result in ISA bus cycles, but MEMR#
and MEMW# pulses are not generated for these cycles. MEMR#/MEMW# pulses are always generated for BIOS-
address transactions as specified by C0A43.
The default pulse width for 8-bit IO commands to the ISA bus is 6 BCLKs. The default pulse width for 16-bit IO
commands to the ISA bus is 3 BCLKs.
(
|
FRAME3 & ~DEVSEL & (PCI_COMMAND == 2, 3, 6, 7, 12, 14, or 15) &
FRAME1 & ~DEVSEL &
Subtractive Versus Medium Decoding
ISA/LPC Bridge And Legacy Logic
ISA Bus
(C0A48[SUB] != 1Xb)
( (PCI_COMMAND == INTERRUPT_ACKNOWLEDGE)
| ISA_HIT
| DMAC_HIT
| IDE_HIT
| USB_HIT
| CONFIG_SPACE_1 & ~C0A48[IDEEN#]
| CONFIG_SPACE_4 & ~C0A48[IUSBEN#] | CONFIG_SPACE_3
| BIOS_ADDR_SPACE) );
CBE_L[2] after being latched during the address phase of the PCI cycle.
The latched address for a Config cycle matches the device and function number for one of the
IC’s configuration spaces, functions 0, 1, 3, and 4.
The pulse after FRAME# is asserted used for medium decoding.
The pulse after FRAME# is asserted used for subtractive decoding.
PCI address and command targets the IDE controller.
PCI address and command targets the an internal ISA bus device including the RTC, the PIT,
the PIC, the IOAPIC, LPC-decoded addresses, or a legacy register.
PCI address and command targets the legacy DMA controller.
The latched state of the CBE_L[3:0] signals during the address phase of the cycle. 2=IO read;
3=IO write; 6=memory read; 7=memory write; 12=memory read multiple; 14=memory read
line; 15=memory write and invalidate; any of these commands may be valid to enable the first
term of the equation.
PCI address and command targets the IC’s USB controller.
BIOS space is defined by C0A43.
& ~C0A48[DMAEN#]
& ~C0A48[IDEEN#]
& ~C0A48[IUSBEN#] | CONFIG_SPACE_0
Preliminary Information
AMD-766
TM
Peripheral Bus Controller Data Sheet
// subtractive window
// medium window
16