tsc693e ETC-unknow, tsc693e Datasheet - Page 86

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

*)
**)
Abreviations used in the timing diagrams :
MATRA MHS
Rev. D (10 Apr. 97)
t55
t56
t57
t58
t59
t60
t61
t62
t63
t66
t68
t69
t70
t71
t73
t74
t75
t78
For the chip select timing the following formula applies:
If (address valid before SYSCLK+) > t9 then (chip select output delay time) = t10
else (chip select output delay time) = t9+t12
DOE* is deasserted on SYSCLK- during store byte/halfword
FAn: Fetch address n,
SAn: Store address n,
FDn: Fetch data n,
SDn: Store data n,
15
4
15
4
15
4
>t1
22
3
0
4
1
100
1000
15
35
20
20
35
TCLK Period Time
TRST* Input Setup
TRST* Input Hold
TMS Input Setup
TMS Input Hold
TDI Input Setup
TDI Input Hold
TDO Output Delay
WDCLK Clock Period Time
DPARIO generation Time including Output Delay
ExtHold, ExtCCV Input Setup
SYSCLK High to Low Output Delay
SYSCLK Low to High Output Delay
Data and checkbits Setup Time MEC during load
Data Valid to MHOLD* Delay when MEC checks parity
and checkbits
DMAAS Input Setup
DMMAS Input Hold
Data, Parity and Checkbits Hold during Load
LAn: Load address n,
TAn: Trapp address n
LDn: Load data n,
TDn: Trapp data n,
TCLK +
TCLK +
TCLK +
TCLK +
TCLK +
TCLK +
TCLK +
Data Valid
SYSCLK+
CLK2+
CLK2+
SYSCLK+
Data Valid
SYSCLK+
SYSCLK-
SYSCLK+
TSC693E
4