tsc693e ETC-unknow, tsc693e Datasheet - Page 40

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
3.15. UART
The MEC includes two full duplex asynchronous receiver transmitters (UARTs).
The data format of the UARTs is eight bits. It is possible to choose between even or odd
parity, or no parity, and between one and two stop bits by programming the MEC
Control Register (see page 51). After system reset odd parity and one stop bit are set.
The baud rate of the UART is set by programming the MEC Control Register (see
page 51). After system reset the baud rate is set to system clock frequency divided by 32
which is probably not a usable baud rate. It follows that the baud rate in the MEC
Control Register must be programmed after system reset.
The UARTs provides double buffering, i.e. each UART consists of a transmitter holding
register, a receiver holding register, a transmitter shift register, and a receiver shift
register. Each of these registers has a width of 8 bits. For each UART a RX and TX
Register (see page 62) is provided. There is also a common UART Status Register
(see page 62).
Figure 9 - removed
The receiver converts serial start bit, data word, parity bit and stop bit(s) into parallel
form. The transmitter converts parallel data into serial form automatically adding start
bit, parity bit, and stop bit(s).
To output a byte on the serial output the following procedure should be followed. First,
the UART Status Register should be read in order to check that the transmitter holding
register (THE, bit 2 and bit 18 respectively for channel A and B) is empty. Otherwise,
the previous byte to be output may be lost (note that the TSE bit is not useful for the
purpose of checking if a character may be written to the RX/TX register). Then, the byte
to be output (RTD, bits 0-7) is written in the RX and TX register. The byte written will
then automatically be transferred to the transmitter send register and converted to serial
form also adding start bit, parity bit, and stop bit(s). The above described sequence can
be part of a trap handler for the UART interrupt.
When a data byte has been received on the serial interface an interrupt is issued to the
IU. The byte received is converted to parallel form and loaded into the receiver data
register. Framing error, i.e. the stop bit is not of correct polarity, parity error, and
overrun error, i.e. the preceding byte has not been read before a complete following byte
is received, are indicated by the bits FE, PE, and OE, respectively in the UART status
register.
A correctly received byte is indicated by the Data Ready bits for channel A and B (DRA,
bit 0 and DRB, bit 16) when reading the UART status register.
The UARTs generate an interrupt each time a data word has been received, a data word
has been sent, and if an error is detected. There is one interrupt from each UART (A and
B) to indicate that data is correctly received or that the transmitter register is empty.
MATRA MHS
Rev. D (10 Apr. 97)
40