tsc693e ETC-unknow, tsc693e Datasheet - Page 14

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
area. In addition, one extra clock cycle is always introduced in the beginning of the cycle
for the external address decoding. Byte, halfword and word access is allowed.
3.2.3. Boot PROM
The MEC allows software to be executed from a single byte-wide PROM. Alternatively,
a full wide EDAC protected (40 bits) PROM can be used. Hereafter this start-up PROM
is called boot PROM.
One extra clock cycle is always introduced in the beginning of the cycle for the address
decoding. The IU supports byte operations on data, but for instruction fetches it needs a
full 32 bit wide word. In the case that byte-wide boot PROM is used (selected by
asserting the PROM8* input pin of the MEC), the MEC performs an 8 to 32 bit
conversion of the boot PROM data during read access. This means that a word access to
byte-wide boot PROM will correspond to four byte fetches. The total number of cycles
required for each word read will then be equal to 4*(1+ no. of boot PROM
waitstates)+2.
When 32-bit wide PROM is used both EDAC and parity bits must be supplied to the
MEC.
During read operations, byte, halfword and word access is allowed. If the boot PROM is
based on EEPROM devices, the MEC supports write access, but note that only byte
write is supported if byte-wide EEPROM is used. The write access possibility is enabled
by asserting the Prom Write Control signal (ROMWRT*).
The following sizes of the boot PROM are allowed: 128 Kbytes, 256 Kbytes,
512 Kbytes, 1 Mbytes, 2 Mbytes, 4 Mbytes, 8 Mbytes and 16 Mbytes. Selection of
PROM size is to be performed by programming the Memory Configuration Register
(see page 51). The default size of the boot PROM after system reset is the minimum
size, 128 Kbytes. The MEC provides one PROM chip select output.
3.2.3.1. Extended PROM
In addition to the boot PROM area, an extended PROM area is reserved in the MEC
memory map. The MEC does not provide any chip select signals for the extended
PROM area, i.e. address decoding must be implemented with external logic. The
extended PROM area is BUSRDY* controlled with the same number of waitstates as
the boot PROM area. In addition, one extra clock cycle is always introduced in the
beginning of the cycle for the external address decoding. The number of cycles is
however always at least two even if the PROM area waitstate value has been
programmed to zero. The same restrictions as for boot PROM apply regarding data
width and write access.
MATRA MHS
Rev. D (10 Apr. 97)
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