tsc693e ETC-unknow, tsc693e Datasheet - Page 32

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

Table 4 - MEC parity handling
RAM and exchange memory
RAM and exchange memory
ROM, 8-bit access
ROM, 40-bit access
MEC registers
IO areas
IO areas
Extended general area
DMA access with DMA parity enabled
DMA access with DMA parity enabled
DMA access with DMA parity disabled
DMA access with DMA parity disabled
G = parity generated, C = parity checked, N= parity not checked nor generated
Note: When a correctable error occurs in the RAM or exchange memory
3.10. Memory Redundancy
The MEC dedicates chip selects for two redundant memory banks for replacement of
faulty banks. A memory bank is a block composed of 32-bit data, parity and a 7-bit
checkcode and controlled with one chip select signal. The size of the redundant memory
banks are dependent of the memory size register.
Exclusion of a faulty memory block and selection of a redundant memory block is
performed by programming the Memory Configuration Register (see page 52). This
remapping has no influence on the performance.
3.11. Synchronous Traps
Memory access error are signaled by the MEC by assertion of the MEXC* signal. This
event will force the IU to vector to either an instruction access exception or a data
access exception, see [RD2].
Upon detecting an instruction or data exception, the IU enters the corresponding trap.
The trap handler software can identify the synchronous fault with the aid from the Error
Handler functions included in the MEC (see paragraph 3.17.).
The MEC is capable of handling 9 different fault events which all will result in a
synchronous trap of the type instruction access exception or data access exception in the
IU by assertion of the MEXC* signal.
MATRA MHS
Rev. D (10 Apr. 97)
MEC generates parity (G) even if parity is enabled.
Accessed memory area
parity enabled
Memory
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
Read
G
C
G
C
G
G
C
G
C
G
C
N
Write
C
C
C
C
C
C
C
C
C
C
G
N
TSC693E
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