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... For Embedded Real time 32-bit Computer MATRA MHS Rev. D (10 Apr. 97) TSC693E Memory Controller User's Manual (ERC32) for SPACE Applications TSC693E 1 ...
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... System Halt Mode................................................................................. 22 3.5.4. Power-Down Mode............................................................................... 23 3.5.5. Error Halt Mode.................................................................................... 23 3.6. Wait-State and Timeout Generator.......................................................... 23 3.7. Memory Access Protection...................................................................... 24 3.7.1. Unimplemented Areas .......................................................................... 24 3.7.2. RAM Write Access Protection.............................................................. 25 3.7.3. Boot PROM Write Protection............................................................... 26 3.8. Register Access Protection...................................................................... 26 3.9. EDAC ...................................................................................................... 27 3.9.1. Check Bit Generator.............................................................................. 28 3.9.2. Syndrome Generator ............................................................................. 29 3.9.3. Syndrome Detector ............................................................................... 30 MATRA MHS Rev. D (10 Apr. 97) TSC693E Page 2 ...
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... UART Interface..................................................................................... 78 4.2.6. Power and Clock Signals ...................................................................... 79 5. ELECTRICAL AND MECHANICAL SPECIFICATION........................ 80 5.1. Maximum Rating and DC Characteristics .............................................. 80 5.1.1. Maximum Ratings................................................................................. 80 5.1.2. Operating Range ................................................................................... 80 5.1.3. DC Characteristics over the Operating Range ...................................... 80 5.1.4. Capacitance Ratings.............................................................................. 81 5.2. Package Description ................................................................................ 81 5.2.1. Pin Assignments.................................................................................... 81 5.2.2. Package Diagram .................................................................................. 82 APPENDIX 1 - TIMING DIAGRAMS MATRA MHS Rev. D (10 Apr. 97) TSC693E 3 ...
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... INTRODUCTION 1.1. Scope This document constitutes a functional specification of iteration two of the TSC693E Memory Controller (MEC) which is an element in the ERC32 microprocessor core intended to function as a User's guide both for the software and hardware developers. The document is divided into the following sections: GENERAL OVERVIEW OF ERC32 A short overview of a typical ERC32 based system ...
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... AD3 32-bit Microprocessor Software Tools Technical Requirements, WDI/1339/FGM/NL, 05-06-1991. AD4 ERC32 Technical Specification, MCD/SPC/0001/SE, issue 7, 1 Apr 1994. 1.2.2. Reference Documents RD1 SPARC Standard Version 7 RD2 TSC691E Integer Unit RD3 TSC692E Floating Point Unit User's Manual MATRA MHS Rev. D (10 Apr. 97) TSC693E 5 ...
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... Random Access Memory RD Reference Document ROM Read Only Memory RTC Real Time Clock SFSRSystem Fault Status Register SW Software TAP Test Access Port TBC To Be Confirmed TBD To Be Defined UART Universal Asynchronous Receiver Transmitter WD Watch Dog MATRA MHS Rev. D (10 Apr. 97) TSC693E 6 ...
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... Signal Names The following conventions are used for signal names: - Signal names are written in capital letters, SIGNALNAME. - Active low signals are named, SIGNALNAME*. 1.4.3. Registers The following convention is used for registers. - Register names are bolded, Register Name. MATRA MHS Rev. D (10 Apr. 97) TSC693E 7 ...
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... Floating Point Unit: TSC692E (called FPU in this document). The processor includes concurrent error detection facilities. - Memory Controller: TSC693E (called MEC in this document), which is a unit consisting of all necessary support functions such as memory control and protection, EDAC, wait state generator, timers, interrupt handler, watch dog, UARTs, and test support ...
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... Ctrl Hold MEC Error Ctrl Check bits Check bits IRQ Figure 1 - ERC32 Computer with typical peripherals MATRA MHS Rev. D (10 Apr. 97) IU BOOT PROM RAM I/O IRQ ATAC External IRQs TSC693E Ctrl FPU Data Address ERC32 9 ...
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... The MEC interfaces directly to the address, data, and control buses of the IU and FPU, requiring no additional components. It also interfaces directly to external memory and I/O units only requiring additional buffers for the address and data bus. The architecture of the MEC is illustrated in Figure 2. MATRA MHS Rev. D (10 Apr. 97) TSC693E 10 ...
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... Config EDAC WaitSt. Bus Timers Arbiter * RTC * One General purpose UARTS Two program- Port mable serial full duplex channels. Figure 2 - MEC architecture TSC693E Errors* Syshalt* Cpuhalt* SysAv / MecErr* IRL(3:0) INTACK Memctrl MemCS* ROMCS* IOctrl IOSel* Mhold* MDS* MEXC* DMAREQ* DMAGNT* AOE/COE/DOE* ...
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... BUSERR* is used to signal erroneous access to the MEC when accessing I/O, exchange memory and extended areas. 3.2.2. RAM The MEC is reprogrammable to interface with a number of different RAM sizes and organisations. The table below shows all possible memory sizes and organisations: MATRA MHS Rev. D (10 Apr. 97) TSC693E 12 ...
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... MEC loads whole word Old checkbits TSC693E Chip org used = chips 64k chips 128k chips 256k chips 512k chips 1M chips 2M chips 4M chips 8M chips 4 5 MEC drives new word ...
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... The number of cycles is however always at least two even if the PROM area waitstate value has been programmed to zero. The same restrictions as for boot PROM apply regarding data width and write access. MATRA MHS Rev. D (10 Apr. 97) TSC693E 14 ...
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... System Fault Status Register (SFSR) of the MEC, which then responds by asserting Error to the interrupt logic. These bits describe system bus error cases, in addition the bus timeout is set if the internal bus time out timer causes abortion. MATRA MHS Rev. D (10 Apr. 97) TSC693E 15 ...
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... IU on the other subwords in the full word, see Figure 4. MATRA MHS Rev. D (10 Apr. 97) BUSRDY* Action H Nothing (not ready) L Data Strobe (ready) H Nothing (not ready) L System Bus Error TSC693E 16 ...
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... The number of waitstates is however always at least one even if the I/O area waitstate value has been programmed to zero. The same no. of waitstates and parity option as for I/O area 3 apply. MATRA MHS Rev. D (10 Apr. 97) DATA BIT 24 16 SAME DATA AS ON BITS SAME DATA AS ON BITS (7:0) (7:0) IU DATA TSC693E DATA 17 ...
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... Parity/EDAC options All data sizes allowed 192M The same settings as for 1) RAM Memory 0 - 16M Parity option All data sizes allowed 0 - 16M As above 0 - 16M As above 0 - 16M As above 1728M The same settings as for 1) I/O area parity/EDAC 1) All data sizes allowed TSC693E 18 ...
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... If no subsequent DMA cycles are to be issued the DMA unit shall remove the DMAREQ* signal as soon as it has fetched the data on read after that it has received MATRA MHS Rev. D (10 Apr. 97) TSC693E 19 ...
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... Thus the DMA is granted access to the system bus provided this has been enabled by the IU in the MEC. In other words the IU has the capability to prevent DMA accesses by disabling DMA in the MEC. 3.5. Execution Modes The execution modes of the ERC32 as controlled by the MEC is shown in Figure 5. MATRA MHS Rev. D (10 Apr. 97) TSC693E 20 ...
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... System halt mode is entered upon assertion of SYSHALT* and exited when SYSHALT* is deasserted. Figure 5 - ERC32 Execution Modes MATRA MHS Rev. D (10 Apr. 97) System Reset DMA (RUN) 1) SYSTEM HALT SYSTEM SYSTEM 1) HALT HALT SYSTEM HALT 1) POWER DOWN TSC693E ERROR HALT DMA 1) (Power down) 21 ...
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... CPUHALT* output is asserted, freezing IU/FPU execution. All timers are halted and the UART operation is stopped. The MEC allows DMA accesses during system halt mode, in which DMA has permanent access to the system, i.e. DMAGNT* is asserted immediately on DMA request. When SYSHALT* is deasserted, the previous mode is entered. MATRA MHS Rev. D (10 Apr. 97) TSC693E 22 ...
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... MEC Control Register. 3.6. Wait-State and Timeout Generator It is possible to control the wait state generation by programming a Waitstate Configuration Register (see page 55) in the MEC. The maximum programmable number of wait-states is applied as default at reset. MATRA MHS Rev. D (10 Apr. 97) TSC693E 23 ...
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... The bus timeout counter will start when the access is initiated. If the bus ready signal is not asserted before a valid number of system clock cycles, a memory exception will occur. For further actions taken see paragraph 3.17. MATRA MHS Rev. D (10 Apr. 97) TSC693E 24 ...
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... The segments are only active during RAM access, i.e. they can only be mapped to the RAM area. If both the SE and UE bits of the Segment Base Register are cleared, write protection is effectively disabled for that segment. MATRA MHS Rev. D (10 Apr. 97) TSC693E 25 ...
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... DMA mode if the CPUHALT* is active and only as full 32-bit size data write accesses to the registers register access violation is performed by the IU, the memory exception output is asserted register access violation is performed by the DMA, the memory exception output (MEXC*) and the DMA access error interrupt output are asserted. MATRA MHS Rev. D (10 Apr. 97) TSC693E 26 ...
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... Single Event Upset induced) the data has to be read and re-written by software as the MEC does not automatically write back the corrected data nibble is defined as a bit group of four within the data word, D(3:0), D(7:4) etc. MATRA MHS Rev. D (10 Apr. 97 the data word as a non-correctable error. TSC693E 27 ...
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... D31 xor D30 xor D29 xor D28 xor D27 xor D23 xor D22 xor D19 xor D18 xor D17 xor D16 xor D15 xor D11 xor D07 xor D02 xor D01 DPARIO = Odd parity over D31 not (D31 xor D30 xor .... xor D01 xor D00) MATRA MHS Rev. D (10 Apr. 97) TSC693E 28 ...
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... CB5(Read Data) xor Read Checkbit5 SY4 = CB4(Read Data) xor Read Checkbit4 SY3 = CB3(Read Data) xor Read Checkbit3 SY2 = CB2(Read Data) xor Read Checkbit2 SY1 = CB1(Read Data) xor Read Checkbit1 SY0 = CB0(Read Data) xor Read Checkbit0 MATRA MHS Rev. D (10 Apr. 97) TSC693E 29 ...
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... Corrected Data = Data xor "000100000000000000000000000000000" when "01011011" => Corrected Data = Data xor "001000000000000000000000000000000" when "01101101" => Corrected Data = Data xor "010000000000000000000000000000000" when "00000000" => Corrected Data = Data xor "100000000000000000000000000000000" when "10000000" => Corrected Data = Data xor "000000000000000000000000000000000" (no error) MATRA MHS Rev. D (10 Apr. 97) TSC693E 30 ...
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... Towards I/O, the MEC can be programmed to use no parity or only parity. The signal used for the parity bit is DPARIO. This pin is used by the MEC to check and generate the odd parity over the 32-bit data bus according to Table 4 below. MATRA MHS Rev. D (10 Apr. 97) TSC693E 31 ...
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... IU by assertion of the MEXC* signal. MATRA MHS Rev. D (10 Apr. 97) Memory Read Write parity enabled No G Yes Yes C Yes Yes Yes Yes TSC693E ...
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... The following interrupts, representing asynchronous traps, asserts the Interrupt Request Level (IRL) inputs of the processor: Watch Dog time-out This interrupt occurs if the watchdog timer times out. DMA time-out This interrupt occurs if the DMA session exceeds permitted time. MATRA MHS Rev. D (10 Apr. 97) TSC693E 33 ...
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... The interrupts in the IPR are cleared automatically when the interrupt is acknowledged. The MEC will sample the trap address in order to know which bit to clear. Upon receiving an interrupt, external or forced, the MEC issues a request on its IRL outputs to the IU with the corresponding interrupt level. If two or more interrupts occur MATRA MHS Rev. D (10 Apr. 97) TSC693E 34 ...
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... Masked Hardware errors MATRA MHS Rev. D (10 Apr. 97) Priority Trap Type Interrupt level/no 13 0x1F 15 14 0x1E 14 15 0x1D 13 16 0x1C 12 17 0x1B 11 18 0x1A 10 19 0x19 9 20 0x18 8 21 0x17 7 22 0x16 6 23 0x15 5 24 0x14 4 25 0x13 3 26 0x12 2 27 0x11 1 TSC693E 35 ...
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... Real Time Clock Timer has an 8-bit scaler while the General Purpose Timer has a 16-bit scaler providing a wider range. While the signal CPUHALT* is active, the timers are temporary halted. MATRA MHS Rev. D (10 Apr. 97) Set Preload The Counter Zero indication TSC693E Interrupt 36 ...
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... Register <Scaler> (see page 58). The timer count load value is programmable in General Purpose Timer Program Register <Counter> (see page 58). The value of these registers will not be altered unless reprogrammed or reset. After system reset the General Purpose Timer is not running and must be programmed as required. MATRA MHS Rev. D (10 Apr. 97) TSC693E 37 ...
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... MEC. The Watchdog is temporary halted when the CPUHALT* signal is active. Figure 7 explains all the states and transitions of the watchdog timer. MATRA MHS Rev. D (10 Apr. 97) TSC693E 38 ...
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... Figure 7 - Watchdog timer states and transitions MATRA MHS Rev. D (10 Apr. 97) System / processor reset WD Init Watchdog Program (New value) default value Trap Door set WD disabled WD enabled normal mode Watchdog Timeout acknowledge (New value) WD Reset timer enabled Reset Timeout WD halted TSC693E Interrupt Processor reset 39 ...
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... The UARTs generate an interrupt each time a data word has been received, a data word has been sent, and if an error is detected. There is one interrupt from each UART (A and B) to indicate that data is correctly received or that the transmitter register is empty. MATRA MHS Rev. D (10 Apr. 97) TSC693E 40 ...
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... If a memory exception event occurs the System Fault Status Register (see page 60) is updated and reflects the type and location of parity errors. All external parity checking can be disabled using the NOPAR* signal. MATRA MHS Rev. D (10 Apr. 97 TSC693E 41 ...
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... MEC hardware error will cause the MEC to assert the MECHWERR* and SYSERR* signals. The memory exception output (MEXC*) is not asserted in this case. MATRA MHS Rev. D (10 Apr. 97) & MCR Error Mask & TSC693E MCR Reset Halt >1 SYSERR* Masked Hardware Error ...
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... A detected comparison error (CMPERR) from either of the checking devices will cause the MEC to assert the SYSERR* signal if the comparison error is unmasked. MATRA MHS Rev. D (10 Apr. 97) Master Checker on IU and FPU FPU CMPERR HWERR CFPU CMPERR HWERR TSC693E MEC IUCMPERR IUHWERR IUERR FPUCMPERR SYSERR FPUHWERR SYSAV MECHWERR 43 ...
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... With data access is meant an IU operand fetch or a DMA, i.e. the ASI bits indicate an ongoing data load/store cycle. The following figure shows all possible latching scenarios for the SFSR and FAR registers. MATRA MHS Rev. D (10 Apr. 97) TSC693E 44 ...
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... Rev. D (10 Apr. 97) NO ERROR All errors cleared All errors cleared SYNCH. EDAC DATA CORRECTABLE ERROR ERROR Synchronous data error detected for IU or DMA TSC693E EDAC Corectable error detected for IU and DMA EDAC Corectable error detected for IU and DMA 45 ...
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... FAR : Failing Address Register * SFSR is updated at the time of Watchdog interrupt while ERSR is only updated if the Watchdog elapsed causes a halt or reset. MATRA MHS Rev. D (10 Apr. 97) SFSR FAR SFSR ERSR FAR TSC693E 46 ...
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... When the interrupt is acknowledged, the MEC will automatically clear the bit in the IPR corresponding to the trap address as described above. When "Interrupt test" is enabled: - Setting a bit in IFR will force the corresponding interrupt not masked in IMR. MATRA MHS Rev. D (10 Apr. 97) TSC693E 47 ...
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... CLK2 negative edge which means that the CLK2 duty cycle has a direct impact on the system performance. When interfacing peripherals (I/O interface, DMA interface etc highly recommended that only SYSCLK rising edge is used as reference as far as possible. CLK2 should be used as input to the MEC only. MATRA MHS Rev. D (10 Apr. 97) TSC693E 48 ...
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... Unimplemented area 01F8 009C 01F8 00A0 01F8 00A4 Unimplemented area 01F8 00A8 - 01F8 00AC 01F8 00B0 Unimplemented area 01F8 00B4 - 01F8 00CC 01F8 00D0 Unimplemented area 01F800D4 - 01F800DC 01F8 00E0 01F8 00E4 01F8 00E8 Unimplemented area 01F8 00EC - 01FF FFFF TSC693E 49 ...
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... Certain registers below are not true registers in the sense that they only correspond to a write operation with any data. Any data may be used when writing to these registers. Nevertheless, they are part of the register memory map and therefore included. MATRA MHS Rev. D (10 Apr. 97) TSC693E 50 ...
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... UART parity enable 1 : parity enabled parity 1 UART parity 1 : odd parity 0 : even parity 0 UART stop bits 1 : two stop bits 0 : one stop bit 1 UART clock supply 1 : system clock 0 : external clock 00000001 UART scaler, ( 255: Divide factor 0: stops the UART clock TSC693E r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w ...
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... Mbyte 100 : 4 Mbyte 101 : 8 Mbyte 110 : 16 Mbyte 111 : 32 Mbyte 0 RAM memory parity protected 1 : enabled 0 : disabled 0 RAM EDAC protected 1 : enabled 0 : disabled (Note: When EDAC is enabled parity is enabled independent of RPA) 0 Not used 1 PROM write function 1 : enabled if external ROMWRT* present 0 : disabled TSC693E r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w 52 ...
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... Kbyte 101 :128 Kbyte 110 :256 Kbyte 111 :512 Kbyte 0 Exchange memory parity protected 1 : enabled 0 : disabled 0 Exchange memory EDAC protected 1 : enabled 0 : disabled (Note: When EDAC is enabled parity is enabled independent of EPA) 0 Exchange memory exists 1 : exists 0 : exists not 00 Not used TSC693E r r/w r r/w r/w r/w r ...
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... Yes (Note: MEC checks parity (Note: MEC generated parity) 0 Not used 0 Not used 0000 I/O unit<3> size. Coded as I/O unit<0> 0 I/O unit<3> enabled 1 : enabled 0 : disabled 0 Parity supplied by I/O unit <3> Yes (Note: MEC checks parity (Note: MEC generated parity) 0 Not used 0 Not used TSC693E r/w r/w r/w r r/w r/w r r/w r/w r r/w r/w r/w r ...
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... WS 1111 IO 2 read/write, no. of waitstates. 0000 : "0 WS" See Note 1) below 0001 : 0 WS 0010 : 1111 : 14 WS 1111 IO 3 read/write, no. of waitstates. 0000 : "0 WS" See Note 1) below 0001 : 0 WS 0010 : 1111 : 14 WS TSC693E r ...
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... Not used 01F8 0048 H Reset value Function 0 Not used 0h Pending interrupts bit interrupt 1 pending bit interrupt 1 not pending .. bit interrupt 15 pending bit interrupt 15 not pending 0h Not used TSC693E r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r ...
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... Not used Reset value Function FFFFh Preset 16-bit counter value FFh Preset 8-bit scaler value FFh Preset 8-bit reset counter value (WDS+1) (WDR+1)/WDCLK 01F8 0064 H TSC693E r/w r r r/w r r ...
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... Programmed 8-bit scaler value 0h Not used Reset value Function FFFFFFFFh Down counting 32-bit counter 01F8 0088 H Reset value Function FFFFFFFFh Programmed 32-bit counter value 01F8 008C H Reset value Function FFFFh Down counting 16-bit scaler 0h Not used TSC693E r/w r r r/w r r ...
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... Real Time Clock Scaler enable 1 : enable counting 0 : hold scaler (and counter) 0 Real Time Clock Scaler load 1 : load scaler with preset value and start if enabled function 0h Not used TSC693E r r ...
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... Not used DMA RAM/ROM/Register User I/O/Exchange Supervisor I/O/Exchange DMA I/O/Exchange User Data RAM/ROM/Register Supervisor Data RAM/ROM/Register Not used Not used DMA RAM/ROM/Register User I/O/Exchange Supervisor I/O/Exchange DMA I/O/Exchange Reset value Function 0h Failing address TSC693E r/w r r/w r/w r r/w r/w r r/w r ASI 0xA 0xB - - Do not care ...
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... EDAC test enable 0: Testing disabled 1: Memory test enabled 0 Parity test 1 : test enabled 0 : test disabled 0 Interrupt Force Register Write Enable 1 : enabled 0 : disabled 0 Error Write Enable 1: Write to Error and Reset Status Register enabled 0: Write to Error and Reset Status Register disabled 0 Not used TSC693E r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r r/w ...
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... Data Ready in channel B 1 Transmitter B Send Register Empty (no data to send) 1 Transmitter B Holding register Empty (ready to load data) 0 Not used 0 Framing Error in receiver B 0 Parity Error in receiver B 0 Overrun Error in receiver B 0 Clear UART B (bit read as zero) 0h not used TSC693E r/w r/w r r/w r r/w r ...
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... Read Access I Write Enable I Advanced Write MEC Control Parity O Address Output Enable O Control Output Enable O Data Output Enable O Bus Hold O Memory Data Strobe O Memory Exception TSC693E Par Pin Type P TTL P TTL P TTL P TTL P TTL P TTL/CMOS P TTL/CMOS TTL TTL TTL TTL ...
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... I IU Hardware Error I IU Comparison Error I FPU Hardware Error I FPU Comparison Error O MEC Hardware Error O System Error O System Availability I System Halt I No Parity TSC693E CMOS CMOS TTL/CMOS CMOS TTL CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS ...
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... Receive Data channel B O Transmit Data channel A O Transmit Data channel B I Double Frequency Clock O System Clock I Main internal VCC I Output driver VCC I Main internal VSS I Output driver VSS TSC693E TTL CMOS TTL TTL TTL TTL CMOS TTL TTL TTL CMOS CMOS TTL TTL/CMOS 65 ...
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... DPARIO - Data Bus Parity Input/Output (bi-directional) This pin is used by the MEC to check and generate the odd parity over the 32-bit data bus during write cycles. A DMA unit must supply this bit in case DMA parity is enabled. See also Table 4 on page 32. MATRA MHS Rev. D (10 Apr. 97) TSC693E 66 ...
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... DXFER is sent out unlatched and is latched in the MEC before it is used. A DMA unit must supply this signal during a DMA session. MATRA MHS Rev. D (10 Apr. 97) TSC693E 67 ...
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... MEC before it is used. To avoid writing to memory during memory exceptions, WE* is internally qualified by MHOLD* and MEXC*. A DMA unit must supply this signal during a DMA session, asserted low for write and deasserted high for read accesses. MATRA MHS Rev. D (10 Apr. 97) TSC693E 68 ...
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... During nominal execution with the IU as bus master, MDS* is asserted by the MEC to enable the clock to the instruction register of the IU (during an instruction fetch the load result register (during a data fetch) while the pipeline is frozen with an MHOLDA/B*. MATRA MHS Rev. D (10 Apr. 97) TSC693E 69 ...
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... MHOLD* - Memory Bus Hold (output) MHOLD* is used to freeze the clock to both the IU and floating-point unit during a cache miss (for systems with cache memory) or when accessing a slow memory generated by the MEC to insert wait states during memory or I/O accesses. MATRA MHS Rev. D (10 Apr. 97) TSC693E 70 ...
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... PROM connected to the D[7:0] signals. The MEC will perform a 8-bit to 32-bit conversion when the IU reads from the PROM. There is no EDAC or parity checking on accesses to the PROM when PROM8 is asserted, and EDAC and parity bits must be supplied by the PROM when PROM8 is deasserted. MATRA MHS Rev. D (10 Apr. 97) TSC693E 71 ...
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... RAMBEN* - RAM Buffer Enable (output) RAMBEN* is asserted during memory accesses to RAM intended to be used as buffer enable for data and check bit buffers in the RAM. MATRA MHS Rev. D (10 Apr. 97) TSC693E 72 ...
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... IOSEL*[3: Chip Select (output) These four select signals are used to enable one of four possible I/O address areas. IOWR Write (output) IOWR* is asserted during write operations to the I/O area, extended I/O area and the exchange memory area. MATRA MHS Rev. D (10 Apr. 97) TSC693E 73 ...
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... DMAREQ issued by a unit requesting the access to the processor bus as a master. DMAGNT* - DMA Grant (output) DMAGNT* is generated by the MEC as a response to a DMAREQ*. DMAGNT* is sent after that the MEC has asserted BHOLD* and deasserted AOE*, DOE*, and COE* for holding and three-stating the IU. MATRA MHS Rev. D (10 Apr. 97) TSC693E 74 ...
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... RESET* for a minimum of sixteen clock cycles. SYSRESET* must be asserted for a minimum of four clock cycles. RESET* - Reset (output) RESET* will be asserted when the IU and the FPU synchronously reset. This occurs when either SYSRESET* is asserted or the MEC initiate a reset due to an error or a programming command. MATRA MHS Rev. D (10 Apr. 97) TSC693E 75 ...
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... This output is asserted whenever an unmasked error is set in the ERSR register. It stays asserted until the ERSR is cleared. The error can originate from either the IU, the FPU, or the MEC itself. SYSERR* is used to signal to the system outside the ERC32 based computer. MATRA MHS Rev. D (10 Apr. 97) TSC693E 76 ...
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... IU, the FPU and possibly other units in the system. 4.2.4. Test Access Port Signals The following Test Access Port interface (IEEE standard 1149.1) is used to perform boundary scan for test and debugging purposes. TCK - Test Clock (input) Test clock for scan registers. MATRA MHS Rev. D (10 Apr. 97) TSC693E 77 ...
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... RXB is the serial data input for channel B of the UART. TXA - Transmit Data channel A (output) TXA is the serial data output for channel A of the UART. TXB - Transmit Data channel B (output) TXB is the serial data output for channel B of the UART. MATRA MHS Rev. D (10 Apr. 97) . SYSCLK TSC693E 78 ...
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... VSSI, VSSO - Ground (inputs) These pins provide ground return for the power signals. Ground is supplied on different buses to match the power signals to each section: VSSO pins for the output driver bus; VSSI pins for the main internal circuitry bus. MATRA MHS Rev. D (10 Apr. 97) TSC693E 79 ...
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... V to +7.0 V [2] Ambient Temperature - 125 C Test Conditions Vcc=Min, Ioh=-2.0mA Vcc=Min Vcc=Max, Vss VIN Vcc Vcc=Max, Vss Vout Vcc Vcc=Max, Vout=0V Vcc=5V, f=20 MHz Vcc=5V, f=0 MHz TSC693E Vcc 5 V ±10% Min Max Units 3.7 V 0.5 V 2.1 Vcc V -0.5 0 -30 -350 mA - 100 mA ...
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... OE1* 212 INULL 224 PROM8* 146 IOBEN* 118 RAMBEN* 107 IOSEL0* 116 RESET* 3 IOSEL1* 115 RD 216 IOSEL2* 112 ROMBEN* 108 TSC693E Signal Pin Signal Pin ROMCS* 111 VCCO15 26 ROMWRT * 251 VCCO16 20 RXA 186 VCCO17 14 RXB 184 VSSI1 192 SIZE0 199 ...
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... Package Diagram MATRA MHS Rev. D (10 Apr. 97) TSC693E 82 ...
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... TIMING DIAGRAMS MATRA MHS Rev. D (10 Apr. 97) APPENDIX 1 (SYSCLK @ 10 MHz) TSC693E 1 ...
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... External Error with Reset Timing 42. External Error with CPUHALT Timing 43. Internal MEC Error with Reset Timing 44. Internal MEC Error with CPUHALT Timing 45. Edge Triggered Interrupt Timing 46. Level Triggered Interrupt Timing MATRA MHS Rev. D (10 Apr. 97) TSC693E Issue ...
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... NOPAR, ROMWRT*, PROM8* Input Setup Time t50 4 NOPAR, ROMWRT*, PROM8* Input Hold Time t53 15 APAR, ASPAR, IMPAR Input Setup Time t54 4 APAR, ASPAR, IMPAR Input Hold Time MATRA MHS Rev. D (10 Apr. 97) TSC693E Reference Edge SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK+ SYSCLK- Address Valid SYSCLK+ SYSCLK+ CLK2+ (lo->hi), CLK2- (hi->lo) ...
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... FAn: Fetch address n, SAn: Store address n, FDn: Fetch data n, SDn: Store data n, MATRA MHS Rev. D (10 Apr. 97) LAn: Load address n, TAn: Trapp address n LDn: Load data n, TDn: Trapp data n, TSC693E TCLK + TCLK + TCLK + TCLK + TCLK + TCLK + TCLK + Data Valid SYSCLK+ CLK2+ ...
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... CLK2 t69 SYSCLK MATRA MHS Rev. D (10 Apr. 97 t70 t69 Figure 1) CLK2 to SYSCLK Skew TSC693E t70 5 ...
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... FD1 LD1 FCB1 LCB1 Figure 2) RAM Load-Store Sequence at 0 Waitstates with EDAC and/or Parity Protection TSC693E SA1 FA2 t11 t13 t14 t15 t15 t15 t15 t20 t19 SD1 t23 ...
Page 89
... Rev. D (10 Apr. 97) 1 FA2 LA1 t8 t8 t10 t9 t12 t13 t13 t14 t16 t16 t26 t26 t37 t37 t71 t71 Figure 3) RAM Load at 1 waitstate with EDAC and/or Parity Protection TSC693E 2 3 FA2 FA3 t8 t14 t16 t26 t37 t78 LD1 FD2 t78 LCB1 FCB2 4 7 ...
Page 90
... MHOLD* D (31:0),DPARIO FD1 CB(6:0) FCB1 MATRA MHS Rev. D (10 Apr. 97) 2 SA1 SA1 t15 t15 t15 t26 t26 t19 SD1 t23 SCB1 Figure 4) RAM Store at 1 waitstate with EDAC and/or Parity Protection TSC693E 3 4 FA2 FA3 t8 t11 t13 t14 t15 t20 t24 5 8 ...
Page 91
... Rev. D (10 Apr. 97 FA2 FA2 t8 t11 t13 t13 t13 t16 t16 t16 t26 t73 0H t71 t78 LD1 ERROR FD2 LCB1 FCB2 Figure 5) RAM Load at 0 waitstate with Correctable Error TSC693E 3 4 FA2 FA3 t8 t26 t37 t37 t43 6H t21 t22 LD1 OK FD2 FCB2 9 ...
Page 92
... MATRA MHS Rev. D (10 Apr. 97 FA2 FA2 t8 t13 t13 t16 t16 t26 t73 t71 t78 LD1 ERROR FD2 t71 t78 LCB1 FCB2 Figure 6) RAM Load with Uncorrectable Error TSC693E 3 4 FA2 FA3 t8 t26 t37 t37 t25 t25 FD2 FCB2 10 ...
Page 93
... OE* MHOLD* MDS* MEXC* D (31:0),DPARIO FD1 CB(6:0) FCB1 MATRA MHS Rev. D (10 Apr. 97 FA2 FA2 t8 t8 t13 t16 t26 t37 Figure 7) RAM Load at 1 Waitstate with Access Violation TSC693E 3 4 FA2 FA3 t11 t13 t16 t26 t37 t25 FD2 FCB2 t8 t25 11 ...
Page 94
... Rev. D (10 Apr. 97 SA1 SA1 SA1 t8 t9 t10 t12 t13 t13 t14 t26 Due to the violation no data is stored FD1 SD1 Figure 8) RAM Store at 1 waitstate with Access Violation TSC693E SA1 FA2 TA1 t8 t11 t13 t14 t26 t37 t37 t25 t25 FD2 12 ...
Page 95
... MATRA MHS Rev. D (10 Apr. 97 SA1 SA1 FA2 t10 t13 t26 t26 t37 t37 t25 t25 Due to the violation no data is stored SD1 Figure 9) RAM Store at 0 waitstate with Access Violation TSC693E TA1 TA2 t11 t13 t14 FD2 TD1 TD2 13 ...
Page 96
... SA1 SA1 00/01 00/01 00/01 t14 t14 t16 t16 t26 t27 t20 t19 t71 IU drives subword Old data t71 Old CB Figure 10) RAM Store Byte/Halfword with No Error / Correctable Error TSC693E SA1 FA2 00/01 10 t11 t15 t15 t15 t15 t26 t27 t78 t21 t22 New data ...
Page 97
... SA1 00/01 00/01 00/01 t14 t14 t16 t16 t27 t26 t20 t78 t19 t71 IU drives subword Old data t78 t71 Old CB Figure 11) RAM Store Byte/Halfword with Uncorrectable Error TSC693E SA1 SA1 FA2 00/01 00/01 10 t11 t27 t26 t37 t37 t25 t25 t21 t22 New data ...
Page 98
... MATRA MHS Rev. D (10 Apr. 97 DSA1 DSA2 11 11 t15 t15 t15 t15 t26 t19 t20 DSD1 DSD2 t23 t24 DCB1 Figure 12) RAM Store Double TSC693E 4 5 DSA2 FA2 FA3 t11 t14 t16 t26 t20 t19 FD2 DCB2 FCB2 16 ...
Page 99
... DSA1 DSA2 DSA2 t15 t15 t15 t15 t26 t19 t20 DSD1 DSD2 t23 t24 DCB1 Figure 13) RAM Store Double with exception in 2:nd word TSC693E DSA2 FA2 11 10 t11 t14 t16 t26 t37 t37 t25 t25 DCB2 TA1 10 FD2 FCB2 ...
Page 100
... ACCESS OF BYTE 2 AND 1 ARE NOT SHOWN HERE ACCESS OF BYTE 2 AND 1 ARE NOT SHOWN HERE FA2 FA2 FA2 FA2 t17 00 01/10 t78 t71 LD1 BYTE 3 BYTE 2/1 Figure 14) PROM bytewide Load at 2 waitstates TSC693E FA2 FA2 FA2 t8 t11 t13 t13 t13 t16 ...
Page 101
... BA(1:0) MHOLD* D (7:0) FD1 MATRA MHS Rev. D (10 Apr. 97) 2 SA1 SA1 00 00 t10 t15 t15 BYTE ADDRESS t26 t26 t19 SD1 Fig 15) PROM Bytewide Store TSC693E 3 4 FA2 FA2 t11 t13 t13 t13 t13 t14 t16 t17 t20 FD2 19 ...
Page 102
... MATRA MHS Rev. D (10 Apr. 97 LA1 FA2 FA2 t8 t10 t13 t13 t16 t26 PROMtpd FD1 PROMtpd FCB1 Fig 16) PROM 40 bit wide load TSC693E FA2 FA3 t11 t13 t13 t16 t26 t37 t37 t78 t71 LD1 FD2 t78 t71 ...
Page 103
... Rev. D (10 Apr. 97 SA1 SA1 SA1 t10 t13 t13 t14 t15 t15 t16 t26 IUDATAtpd FD1 LD1 t23 FCB1 Fig 17) PROM 40 bit wide store TSC693E FA2 FA3 t11 t13 t13 t14 t15 t15 t16 t26 IUDATAhold FD2 t20 LCB1 FCB2 21 ...
Page 104
... CLK2 SYSCLK A (31:0) FA1 ASI(7:0) 09H SIZE(1:0) 10 ALE* DXFER WRT RD WE* OE* D (31:0), DPARIO FD0 CB(6:0) FCB0 MATRA MHS Rev. D (10 Apr. 97 LA1 FA2 0BH 09H 10 t16 t21 FD1 LD1 FCB1 Fig 18) MEC Register Load TSC693E 2 FA3 09H 10 10 t16 t22 FD2 FCB2 22 ...
Page 105
... WRT RD WE* DIR OE* D (31:0), DPARIO FD0 CB(6:0) FCB0 MATRA MHS Rev. D (10 Apr. 97 SA1 SA1 0BH 0BH 10 10 t14 t16 IUDATAtpd FD1 FCB1 Fig 19) MEC Register Store TSC693E 2 3 FA2 09H 10 t14 t16 t19 t20 IUDATAhold SD1 FCB2 FA3 09H 10 FD2 23 ...
Page 106
... Rev. D (10 Apr. 97 Addr Wait1 Addr Wait1 Addr Wait2 Addr Wait2 FA2 FA2 t8 t10 t13 t16 t26 t38 EMEMtpd Fig 20) Exchange Memory Load with no Parity or EDAC Protection TSC693E 3 4 Load Load FA2 FA3 t8 t11 t13 t16 t26 t37 t37 t39 t71 t78 ...
Page 107
... Addr Wait1 Addr Wait1 Addr Wait2 Addr Wait2 SA1 SA1 t10 t13 t26 t38 t39 t19 IUDATAtpd SD1 t23 Fig 21) Exchange Memory Store with EDAC and/or Parity Protection TSC693E Store 1 Store 1 Store 2 Store 2 SA1 FA2 t11 t13 t14 t15 t15 t15 ...
Page 108
... Addr Wait1 Busy N+1 Cycl. Busy N+1 Cycl. WS Cycl. WS Cycl. FA2 FA2 t8 t26 t39 t39 t38 t38 EMEMtpd t66 Fig 22) Exchange Memory Load Busy with EDAC and/or Parity Protection TSC693E Load Load FA2 FA2 t8 t11 t13 t16 t26 t37 t37 t71 t78 ...
Page 109
... Addr Wait2 Busy N+1 Cycl. Busy N+1 Cycl. SA1 SA1 SA1 t26 t39 t38 t38 t19 IUDATAtpd SD1 t23 Fig 23) Exchange Memory Store with Busy and with EDAC and/or Parity Protection TSC693E Store 1 Store 1 Store 2 Store 2 SA1 FA2 t11 t13 t14 t15 t15 ...
Page 110
... Rev. D (10 Apr. 97 Wait1 Wait1 Wait2 Wait2 Wait3 Wait3 t5 FA2 FA2 FA2 t8 t18 t13 t26 t16 IOtpd Fig 24) IO Load at 3 waitstates TSC693E Load Load Wait 4 Wait 4 FA2 FA2 FA3 t8 t18 t13 t26 t37 t37 t16 t78 t71 LD1 ...
Page 111
... Rev. D (10 Apr. 97 Wait1 Wait1 Wait 2 Wait 2 Store 1 Store 1 SA1 SA1 SA1 t18 t15 t26 t19 IUDATAtpd LD1 Fig 25) IO Store at 2 waitstates TSC693E Store 2 Store 2 FA2 FA3 t18 t13 t14 t15 t26 t16 t20 FD2 FA4 FD3 29 ...
Page 112
... Wait1 Wait1 Busy Waiting Busy Waiting t5 FA2 FA2 FA2 t8 t18 t13 t26 t16 t38 t39 t38 IOtpd Fig 26) IO Load with Busy TSC693E Load Load Wait 4 Wait 4 FA2 FA2 FA3 t8 t18 t13 t26 t37 t37 t16 t39 t78 t71 ...
Page 113
... Busy waiting Busy waiting Store 1 Store 1 SA1 SA1 SA1 t18 t15 t26 t38 t39 t38 t39 t19 IUDATAtpd STD1 Fig 27) IO Store at 0 waitstates with Busy TSC693E Store 2 Store 2 FA2 FA3 t18 t13 t14 t15 t26 t16 t20 FD2 FA4 FD3 ...
Page 114
... Rev. D (10 Apr. 97 Addr Wait1 Addr Wait1 Busy N+1 Cycl. Busy N+1 Cycl. FA2 FA2 t8 t13 t16 t26 t39 t38 t38 EDATAtpd Fig 28) Extended Area Load with Busy TSC693E 3 4 Load Load FA2 FA2 t8 t13 t16 t26 t37 t37 t39 t71 t78 LD1 FD2 ...
Page 115
... Busy waiting Busy waiting SA1 SA1 SA1 t15 t15 t26 t39 t38 t38 t19 IUDATAtpd SD1 t23 Fig 29) Extended Area Store with Busy TSC693E Store 1 Store 1 Store 2 Store 2 SA1 FA2 t13 t14 t15 t15 t16 t26 t39 t20 IUDATAhold ...
Page 116
... DMAA2 If block transfer t10 t13 t13 t16 t16 t74 t75 t37 t21 t71 t78 DMAD Corrected DMAD DMACB Fig30) DMA RAM Load TSC693E DMAADRhold FA1 FA2 Block transfer t11 t13 t26 Block transfer t27 HIGH: If block transfer ...
Page 117
... DMAD1 t23 DMACB Fig31) DMA RAM Store TSC693E DMAADRhold FA1 Block transfer t11 t13 t13 t14 t26 Block transfer t27 HIGH: If block transfer t74 t75 ...
Page 118
... DMAA1 DMAA2 If block transfer t18 t13 t16 t74 t75 t37 t37 t71 DMAD Fig 32: DMA IO Load TSC693E DMAADRhold FA1 FA2 Block transfer t18 t13 t26 Block transfer t27 HIGH: If block transfer t74 t75 ...
Page 119
... DMAA1 DMAA2 If block transfer t18 t13 t14 t15 t15 t74 t75 t37 t19 DMAD1 t23 DMACB Fig33) DMA IO Store TSC693E DMAADRhold FA1 Block transfer t18 t13 t14 t26 Block transfer t27 HIGH: If block transfer t74 t75 ...
Page 120
... DMAA1 DMAA2 If block transfer t18 t13 t16 t74 t75 t37 t37 t25 t71 DMAD with Exception Fig 34: DMA IO Load with exception TSC693E DMAADRhold FA1 FA2 Block transfer t18 t13 t26 Block transfer t27 HIGH: If block transfer ...
Page 121
... DMAD Corrected DMAD DMACB Fig35) DMA RAM Load with Correctable error TSC693E DMAADRhold FA1 FA2 Block transfer t11 t13 t26 Block transfer t27 HIGH: If block transfer ...
Page 122
... DMAD Invalid DMAD DMACB Fig36) DMA RAM Load with Uncorrectable error TSC693E DMAADRhold FA1 FA2 Block transfer t11 t13 t26 Block transfer t27 HIGH: If block transfer ...
Page 123
... Power down mode until any interrupt detected by MEC Power down mode until any interrupt detected by MEC t27 t40 DMA alowed t42 0H t19 t20 Fig 37) Power down mode after writing to MEC Power Down Register TSC693E N+1 N+2 N+3 FA2 09H t8 t27 t40 t42 t43 ...
Page 124
... IDLE t55 t55 TCLK1 t57 t57 t56 TRST* t58 TMS TDI TDO MATRA MHS Rev. D (10 Apr. 97) Sel. DR Sc. Sel. IR Sc. Capt. IR Shift IR Shift IR t59 t59 t59 t58 t58 t61 t60 t62 Fig 38) TAP Control Timing TSC693E Shift IR Exit IR Update IR IDLE 42 ...
Page 125
... t30 t31 t50 t50 t50 RESET* is asserted for 16 SYSCLK RESET* is asserted for 16 SYSCLK t32 Fig 39) Reset Timing TSC693E 5 15 cycles 17 18 All clocks are not shown All clocks are not shown t36 t35 t32 19 ...
Page 126
... D31:0),DPARIO FDn-2 FDn-1 MATRA MHS Rev. D (10 Apr. 97 FAn+1 FAn t30 t31 t26 t48 t32 FDn Fig 40) Halt Timing TSC693E FAn+1 FAn+2 FAn t26 t48 t32 FDn+1 FDn+2 9 FAn ...
Page 127
... FAn t47 t48 t32 RESET* asserted for 16 SYSCLK cycles RESET* asserted for 16 SYSCLK cycles FDn Fig 41) External Error with Reset Timing TSC693E 13 cycles Not all cyclkes is shown Not all cyclkes is shown ...
Page 128
... SIZE(1:0) 10 ALE* XERR* SYSERR* BHOLD* SYSAV CPUHALT* D31:0),DPARIO FDn-2 MATRA MHS Rev. D (10 Apr. 97 FAn FAn+1 FAn t46 t47 t48 t26 FDn-1 FDn Fig 42) External Error with Halt Timing TSC693E t48 t32 46 ...
Page 129
... RESET* asserted for 16 SYSCLK cycles RESET* asserted for 16 SYSCLK cycles FDn Fig 43) Internal MEC Error with Reset Timing TSC693E 13 cycles Not all cyclkes is shown Not all cyclkes is shown ...
Page 130
... SIZE(1:0) 10 ALE* MECHWERR* SYSERR* BHOLD* SYSAV CPUHALT* D31:0),DPARIO FDn-2 MATRA MHS Rev. D (10 Apr. 97 FAn FAn+1 FAn t48 t48 t26 FDn-1 FDn Fig 44) Internal MEC Error with Halt Timing TSC693E t48 t32 48 ...
Page 131
... Prioritized Prioritized Sampled Sampled Latched Latched Taken Taken FA1 FA2 FA3 FA4 FD0 FD1 FD2 FD3 t43 2 H t45 Fig 45) Edge triggered interrupt Timing TSC693E TTA0 TTA1 TSA0 TSA1 FD4 TD0 TD1 TSD0 t43 0 H t29 t28 9 TSA2 TSD1 ...
Page 132
... Prioritized Prioritized Sampled Sampled Latched Latched FA1 FA2 FA3 FA4 FD0 FD1 FD2 FD3 t43 t45 Fig 46) Level triggered interrupt Timing TSC693E Taken Taken TTA0 TTA1 TSA0 TSA1 FD4 TD0 TD1 TSD0 t43 2 H t43 t43 t29 t28 ...