tsc693e ETC-unknow, tsc693e Datasheet - Page 79

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
4.2.6. Power and Clock Signals
CLK2 - Double Frequency Clock (input)
CLK2 is the input clock to the ERC32 hardware. The frequency of this clock must be
twice the clock frequency used to clock the IU and the FPU. Note that the external
timing of the MEC is affected by the duty cycle of CLK2, as some MEC output signals
are latched with respect to the edges of CLK2.
SYSCLK[1:0] - Clock (output)
SYSCLK is a nominally 50% duty-cycle clock generated by the MEC from CLK2 and is
used for clocking the IU and the FPU as well as other system logic. The SYSCLK is
used as input clock during MEC slave mode.
VCCI, VCCO - Power (inputs)
These pins provide +5 V power to various sections of the MEC. Power is supplied on
two different buses to provide clean, stable power to each section: output drivers, and
the main internal circuitry. VCCO pins supply the output driver bus; and the VCCI pins
supply main internal circuitry.
VSSI, VSSO - Ground (inputs)
These pins provide ground return for the power signals. Ground is supplied on different
buses to match the power signals to each section: VSSO pins for the output driver bus;
VSSI pins for the main internal circuitry bus.
MATRA MHS
Rev. D (10 Apr. 97)
79