tsc693e ETC-unknow, tsc693e Datasheet - Page 44

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
The MEC detects illegal register access, e.g. write to internal register in non supervisor
mode. The memory exception output (MEXC*) is asserted by the MEC, if such an
access is made or if an access to an internal MEC register with erroneous data size is
attempted.
A list of all events (synchronous traps) that cause a MEXC* is found on page 33. Less
critical errors and some other events are called asynchronous traps. These events do not
cause a MEXC* but only an interrupt. A list of all asynchronous traps is found on page
33. The MEC always completes the current cycle when an error is detected and the
MEXC* is generated in the beginning of the next cycle.
Apart from issuing MEXC* and/or interrupt, synchronous and asynchronous events also
cause the MEC to latch some internal registers to hold information about the occurred
error. If a trap event occurs the System Fault Status Register (see page 60) is updated
and reflects the type of error in accordance with the conditions in the table. Also the
Error and Reset Status Register (see page 61) is updated reflecting the type of error in
accordance with the conditions in the table. The associated bus address is latched in the
Failing Address Register (see page 60) in accordance with the conditions in the table.
IU data fault valid and asynchronous fault valid are implemented in the System Fault
Status Register. DMA errors will not overwrite the System Fault Status Register if IU
data fault valid bit is set.
If a data access results in an error, the Failing Address Register is always updated,
even if an error has already been latched before. With data access is meant an IU
operand fetch or a DMA, i.e. the ASI bits indicate an ongoing data load/store cycle.
The following figure shows all possible latching scenarios for the SFSR and FAR
registers.
MATRA MHS
Rev. D (10 Apr. 97)
44