tsc693e ETC-unknow, tsc693e Datasheet - Page 20

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
DRDY*, or when DRDY* is removed on write. The MEC will then remove the
DMAGNT* signal.
It is possible to enable/disable DMA parity by programming the MEC Control
Register (see page 54). The default status after system reset is that DMA parity is
disabled. If DMA parity is enabled it has to be generated during write and possibly
checked by the DMA during read. If DMA parity is not enabled the MEC generates the
parity bit to be stored in the memory in case of write accesses.
Memory access protection is active also during DMA, i.e. attempted write access to
protected memory segments will lead to a memory exception, depending on how the
ASI bits are driven by the DMA unit (user or supervisor mode).
Normally, the same restrictions apply to DMA access of MEC registers as for the IU in
User mode, see page 49. However during system halt (i.e. CPUHALT signal active), the
DMA has the same access rights as the IU in supervisor mode for MEC register access.
With register write access, memory protection could be changed to permit DMA to
access all areas.
The MEC includes a DMA session timeout function preventing the DMA unit to
lockout the IU/FPU by asserting DMAREQ* for a long time. If the DMA Request input
is not deasserted within 1024 system clock cycles after the assertion of DMA Grant, the
memory exception output is asserted and the DMA Grant is removed. The DMA session
timeout function is possible to enable or disable by programming the MEC Control
Register (see page 54). After system reset the timeout function is enabled.
Note that the DMA session timeout function is not the same as a bus timeout, rather an
session scheme timeout. In case of a bus timeout during DMA, the MEC asserts the
Memory Exception output and removes the Bus Grant. For further actions taken see
paragraph 3.17.
3.4. Bus Arbiter
The IU and the FPU always have the lowest priority to the system bus and are denied
access to memory in case of a request from a DMA unit, unless the IU is performing a
locked access or after a DMA exception cycle to allow interrupt handling.
Thus the DMA is granted access to the system bus provided this has been enabled by the
IU in the MEC. In other words the IU has the capability to prevent DMA accesses by
disabling DMA in the MEC.
3.5. Execution Modes
The execution modes of the ERC32 as controlled by the MEC is shown in Figure 5.
MATRA MHS
Rev. D (10 Apr. 97)
20