tsc693e ETC-unknow, tsc693e Datasheet - Page 55

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

Waitstate Configuration Register
MATRA MHS
Rev. D (10 Apr. 97)
Note 1)
Bits
1-0
3-2
7-4
11-8
15-12
19-16
23-20
27-24
31-28
In the I/O area the MEC will always insert one waitstate to wait for the BUSRDY* signal, even when "0 WS" is
programmed in the above register.
Name
RAR
RAW
PRR
PRW
EXRW
IO0RW
IO1RW
IO2RW
IO3RW
Reset value
11
11
1111
1111
1111
1111
1111
1111
1111
01F8 0018 H
Function
RAM read, no. of waitstates.
00 : 0 WS
01 : 1 WS
10 : 2 WS
11 : 3 WS
RAM write, no of waitstates.
00 : 0 WS
01 : 1 WS
10 : 2 WS
11 : 3 WS
PROM read, no. of waitstates.
0000 : 0 WS
0001 : 0 WS
0010 : 1 WS
..
1111 : 14 WS
PROM write, no. of waitstates.
0000 : 0 WS
0001 : 0 WS
0010 : 1 WS
..
1111 : 15 WS
Exchange memory read/write, no. of waitstates.
0000 : 0 WS
0001 : 0 WS
0010 : 1 WS
..
1111 : 15 WS
IO 0 read/write, no. of waitstates.
0000 : "0 WS" See Note 1) below
0001 : 0 WS
0010 : 1 WS
..
1111 : 14 WS
IO 1 read/write, no. of waitstates.
0000 : "0 WS" See Note 1) below
0001 : 0 WS
0010 : 1 WS
..
1111 : 14 WS
IO 2 read/write, no. of waitstates.
0000 : "0 WS" See Note 1) below
0001 : 0 WS
0010 : 1 WS
..
1111 : 14 WS
IO 3 read/write, no. of waitstates.
0000 : "0 WS" See Note 1) below
0001 : 0 WS
0010 : 1 WS
..
1111 : 14 WS
TSC693E
r/w
w
w
w
w
w
w
w
w
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