tsc693e ETC-unknow, tsc693e Datasheet - Page 22

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

3.5.1. Reset Mode
When the SYSRES* input is asserted, the MEC issues a reset of itself and asserts the
RESET* output which is intended be used as reset signal to all other components in the
system (e.g. IU and FPU). The SYSRES* signal shall be applied for at least four clock
cycles.
After the assertion of SYSRES*, the MEC starts the ERC32 system in the reset mode
which means that all MEC registers will be initialized to their reset contents.
The reset signal from the MEC to the IU/FPU etc., RESET*, is minimum 16 clock
cycles long, i.e. it will remain asserted 16 system clock cycles after SYSRES* has been
deasserted.
Reset mode is also entered when the RESET* output of the MEC is asserted from any
other reason than SYSRES* :
When the reset cause is one of the above, all MEC registers will be initialized to their
reset contents except the Error and Reset Status Register (see page 61) which
contains the source of the last processor reset (System reset, software reset, error reset,
watch dog reset). By reading that register upon reset, the IU can determine the cause of
the reset.
3.5.2. Run Mode
In this mode the IU/FPU is executing, all timers of the MEC are running (if software
enabled) and the UART is running.
3.5.3. System Halt Mode
System Halt mode is entered when the SYSHALT* input of the MEC is asserted. The
CPUHALT* output is asserted, freezing IU/FPU execution. All timers are halted and the
UART operation is stopped.
The MEC allows DMA accesses during system halt mode, in which DMA has
permanent access to the system, i.e. DMAGNT* is asserted immediately on DMA
request.
When SYSHALT* is deasserted, the previous mode is entered.
MATRA MHS
Rev. D (10 Apr. 97)
Software reset which is caused by the software writing to a Software Reset
Register (see page 52).
Watchdog reset which is caused by a Watchdog counter timeout (see paragraph
3.14.)
Error reset which is caused by a hardware parity error, EDAC uncorrectable error
or a comparison error (see paragraph 3.17.)
TSC693E
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