tsc693e ETC-unknow, tsc693e Datasheet - Page 43

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

The MEC provides inputs for handling of the following IU and FPU errors (see RD2
and RD3):
A detected error on those inputs will cause the MEC to assert the SYSERR* signal. IU,
FPU and MEC errors are latched even if previous errors are latched.
The MEC also provides inputs for handling of master/slave checking for the IU/FPU.
In Figure 9 a system is shown where master checkers are used on both the IU and FPU.
A detected comparison error (CMPERR) from either of the checking devices will cause
the MEC to assert the SYSERR* signal if the comparison error is unmasked.
MATRA MHS
Rev. D (10 Apr. 97)
- IU Error Mode (IUERR*)
- IU Hardware Error (IUHWERR*)
- IU Comparison Error (IUCMPERR*)
- FPU Hardware Error (FPUHWERR*)
- FPU Comparison Error (FPUCMPERR*)
Figure 9 - Master/Slave configuration on IU and FPU
CIU
IU
CMPERR
CMPERR
HWERR
HWERR
ERROR
ERROR
Master Checker on IU and FPU
CFPU
FPU
CMPERR
CMPERR
HWERR
HWERR
IUCMPERR
IUHWERR
FPUCMPERR
FPUHWERR
IUERR
MEC
MECHWERR
SYSERR
SYSAV
TSC693E
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