tsc693e ETC-unknow, tsc693e Datasheet - Page 38

• Manufacturer Part Number: tsc693e
• Description: Memory Controller
• Manufacturer: ETC-unknow

TSC693E
3.14. Watch Dog
The watch dog function consists of a Watchdog Timer (see page 57). The watch dog is
supplied from a separate external input (WDCLK) which must have a frequency which
is at least three times lower than SYSCLK. This input could be divided by 16 in a
prescaler or routed directly to the scaler of the watch dog as set in the MEC Control
Register (see page 51).
The WDCLK input consists of a Schmitt-trigger to allow clock supply from an external
RC oscillator.
It is possible to program the timer by setting a specific value in the Watchdog Program
and Timeout Acknowledge Register (see page 57). The register consists of one scaler
field and one counter field corresponding directly to the scaler field and the counter field
of the watchdog timer.
After system reset or processor reset, the timer is enabled and starts running. The default
value is the scaler set to maximum and the counter set to maximum. By writing to the
Trap Door Set (see page 57) after system reset, the timer can be disabled. After the
disabling of the watch dog timer a write operation to the Watchdog Program and
Timeout Acknowledge Register (see page 57) starts the timer counting with the value
of the specified fields. Note that the Watchdog cannot be disabled once the Watchdog
Program and Timeout Acknowledge Register has been written.
If the timer is refreshed by writing to Watchdog Program and Timeout Acknowledge
Register (see page 57) before the counter reaches zero value, the timer restarts the
counting with the new delay value. If the timer is not refreshed (reprogrammed) before
the counter reaches zero value, an interrupt is issued to the IU. Simultaneously, the timer
starts counting a reset timeout period with the programmed delay time. Then, if the
timer is acknowledged by writing to Watchdog Program and Timeout Acknowledge
Register (see page 57) with a new programmed value before the reset timeout period
elapses again, the timer restarts counting with the new delay value, but if the timer is not
acknowledged before the reset timeout period elapses, a processor reset is issued by the
MEC.
The Watchdog is temporary halted when the CPUHALT* signal is active.
Figure 7 explains all the states and transitions of the watchdog timer.
MATRA MHS
Rev. D (10 Apr. 97)
38