zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 44

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

11 - 10
BBER
15 - 0
15
15
Bit
Read/Write Address: 002B
Reset Value: 0000
15
14
13
12
Read Address: 002A
Reset Value: 0000
Bit
CNEN
15
BBER
14
14
FS1- 0
CNEN
Name
BEN
AEN
RPS
BEN
14
BBER15 -0
BBER
13
13
Name
H
H
AEN
NREFo Output Enable Bit: When CNEN is low, NREFo output is disabled, i.e., tri-stated.
When CNEN is high, NREFo output is enabled.
B Clocks Output Enable Bit: When BEN is low, the “B Clocks” (C8_B_io and FRAME_B_io)
are disabled, i.e., tri-stated - C8_B_io and FRAME_B_io behave as inputs.
When BEN is high, the “B Clocks” are enabled - C8_B_io and FRAME_B_io behave as
outputs.
A Clocks Output Enable Bit: When AEN is low, the “A Clocks” (C8_A_io and FRAME_A_io)
are disabled, i.e., tri-stated - C8_A_io and FRAME_A_io behave as inputs.
When AEN is high, the “A Clocks” are enabled - C8_A_io and FRAME_A_io behave as
outputs.
Reference Selection Bit: When RPS is low, the preferred reference is the primary reference
(PRI_REF). When RPS is high, the preferred reference is the secondary reference
(SEC_REF).
SEC_REF Frequency Selection Bits: These bits are used to select different clock
frequencies for the secondary reference.
13
H
BBER
12
12
H
Table 18 - Backplane Bit Error Rate Register (BBERR) Bits
RPS
Table 19 - DPLL Operation Mode (DOM1) Register Bits
12
FS1
BBER
0
0
1
1
11
11
Backplane Bit Error Rate Count Bits: These bits refer to the backplane bit
error count. This counter stops incrementing when it reaches the value 0xFFFF.
FS1
11
BBER
10
10
FS0
10
BBER
9
9
Zarlink Semiconductor Inc.
FP1
FS0
9
0
1
0
1
ZL50031
BBER
8
8
FP0
8
44
BBER
SS3
7
7
Secondary Reference
8 kHz
1.544 MHz
2.048 MHz
8.192 MHz (“A Clocks” or “B Clocks”)
7
Description
BBER
SS2
Description
6
6
6
BBER
SS1
5
5
5
BBER
SS0
4
4
4
SP3
BBER
3
3
3
SP2
BBER
2
2
2
SP1
BBER
1
Data Sheet
1
1
SP0
0
BBER
0
0