zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 17

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

For the local interface, the variable delay mode can be programmed through the local connection memory low bits,
LTM2 - LTM0. When LTM2 - LTM0 are programmed to “000”, it is a per-channel variable delay from local input to
local output. When LTM2 - LTM0 are set to “010”, it is a per-channel variable delay from backplane input to local
output.
9.2
In this mode, a multiple page data memory buffer is used to maintain frame integrity in all switching configurations
such that a channel written during frame N is always read out during frame N+2.
For the backplane interface, when BTM2 - BTM0 are programmed to “001”, it is a per-channel constant delay mode
from local input to backplane output. When BTM2 - BTM0 are programmed to “011”, it is a per-channel constant
delay from backplane input to backplane output.
For the local interface, when LTM2 - LTM0 are programmed to “001”, it is a per-channel constant delay mode from
local input to local output. When LTM2 - LTM0 are set to “011”, it is a per-channel constant delay mode from
backplane input to local output.
10.0
The ZL50031 provides a parallel microprocessor interface for non-multiplexed bus structures. This interface is
compatible with Motorola non-multiplexed bus structures. The required microprocessor signals are the 16-bit data
bus (D15-D0), 14-bit address bus (A13-A0) and 4 control lines (CS, DS, R/W and DTA). See Figure 37, "Motorola
Non-Multiplexed Bus Timing" on page 71 for the Motorola non-multiplexed bus timing.
The ZL50031 microprocessor port provides access to the internal registers, the connection and data memories. All
locations provide read/write access except for the Local and Backplane Bit Error Rate registers (LBERR and
BBERR) and Data Memory which can only be read by the users.
10.1
The DTA pin of the microprocessor is driven LOW by internal logic to indicate that a data bus transfer is completed.
When the bus cycle ends, this pin switches to the high impedance state. An external pull-up of between 1 kΩ and
10 kΩ is required at this output.
11.0
The address bus on the microprocessor interface selects the internal registers and memories of the ZL50031. If the
address bit A13 is low, the registers are addressed by A12 to A0 as shown in Table 6 on page 17.
Constant Delay Mode
DTA Data Transfer Acknowledgment Pin
Address Mapping of Memories and Registers
Microprocessor Interface
A13 - A0
0000
0001
0002
0003
0004
0005
0006
0007
Table 6 - Address Map For Internal Registers (A13 = 0)
H
H
H
H
H
H
H
H
Control Register, CR
Device Mode Selection Register, DMS
Block Programming Mode Register, BPM
Reserved
Local Input Bit Delay Register 0, LIDR0
Local Input Bit Delay Register 1, LIDR1
Local Input Bit Delay Register 2, LIDR2
Local Input Bit Delay Register 3, LIDR3
Zarlink Semiconductor Inc.
ZL50031
17
Location
Data Sheet