zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 33

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

18.7
The phase slope or the phase alignment speed is the rate at which a given signal changes phase with respect to an
ideal signal. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally
equal to the value of the final output signal or final input signal. Many telecom standards like Telcordia GR-1244-
CORE state that the phase slope may not exceed a certain value, usually 81 ns/1.327 ms (61 ppm). This can be
achieved by limiting the phase detector output to 61 ppm or less.
When operating in primary master mode, the Phase Slope Limiter Circuit achieves the maximum phase slope of
56 ppm or 7.0 ns/125 µs. When operating in secondary master or slave mode, the output edges follow the input
edges in accordance with the H.110 standard.
18.8
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
For the DPLL, the maximum time interval error is less than 21 ns per reference switch.
18.9
The Phase Lock Time is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the
input and the output signals are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
•
•
•
•
Although a short phase lock time is desirable, it is not always possible to achieve due to other PLL requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time, but better (smaller) phase slope performance (limiter) results in longer lock times. The DPLL loop filter and
limiter were optimized to meet the Telcordia GR-499-CORE jitter transfer and Telcordia GR-1244-CORE phase
alignment speed requirements. Consequently, phase lock time, which is not a standards requirement, is less than
50 seconds.
19.0
During power up, the TRST pin should be pulled low to ensure that the ZL50031 is in the functional mode. An
external pull-down resistor is required on this pin so that the ZL50031 will not enter the JTAG test mode during
power up.
After power up, the contents of the connection memory can be in any state. The ODE pin should be held low after
power up to keep all serial outputs in a high impedance state until the microprocessor has initialized the switching
matrix. This procedure prevents two serial outputs from driving the same stream simultaneously.
During the microprocessor initialization routine, the microprocessor should program the desired active paths
through the switch. The memory block programming feature can also be used to quickly initialize the backplane and
local connection memories.
When this process is completed, the microprocessor controlling the ZL50031 can bring the ODE pin high to
relinquish the high impedance state control.
initial input to output phase difference
initial input to output frequency difference
PLL loop filter
PLL limiter
Phase Slope
Maximum Time Interval Error (MTIE)
Phase Lock Time
Initialization of the ZL50031
Zarlink Semiconductor Inc.
ZL50031
33
Data Sheet