zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 18

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

If A13 is high, the remaining address input lines are used to select the data and connection memory positions
corresponding to the serial input or output data streams as shown in Table 7 on page 19.
The Control register (CR), the Device Mode Selection register (DMS) and the Block Programming Mode register
(BPM) control all the major functions of the device. The DMS and BPM should be programmed immediately after
system power up to establish the desired switching configuration. The Control register is used to select Data or
Connection Memory for microport operations, ST-BUS output frame and clock modes, and to set Memory Block
Programing and Bit Error Rate Testing.
The Control register (CR) consists of the memory block programming bit (MBP) and the memory select bits (MS2-
0). The memory block programming bit allows users to program the entire connection memory in two frames (See
Section 8.0, “Memory Block Programming“ on page 16). The memory select bits control the selection of the
connection memories or the data memories. See Table 8 on page 35 for contents of the Control register.
The DMS register consists of the backplane and the local mode selection bits (BMS, LG31 - LG30, LG21 - LG20,
LG11 - LG10 and LG01 - LG00) that are used to enable various switching modes for the backplane and the local
interfaces respectively. See Table 9 on page 36 for the content of the DMS register.
The BPM register consists of the block programming data bits (LBPD2-0 and BBPD2-0) and the block programming
enable bit (BPE). The block programming enable bit allows users to program the entire backplane and local
connection memories in two frames (see section 8.0, “Memory Block Programming“ on page 16). If the ODE pin is
low, the backplane CT-Bus is in input mode and the local output drivers are in high impedance state. If the ODE pin
Table 6 - Address Map For Internal Registers (A13 = 0) (continued)
A13 - A0
to 001B
to 0026
000A
001C
001D
001E
001F
002A
002B
002C
002D
002E
0008
0009
0020
0021
0022
0027
0028
0029
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Local Input Bit Delay Register 4, LIDR4
Local Input Bit Delay Register 5, LIDR5
Reserved
Backplane Output Advancement Register 0, BOAR0
Backplane Output Advancement Register 1, BOAR1
Backplane Output Advancement Register 2, BOAR2
Backplane Output Advancement Register 3, BOAR3
Local Output Advancement Register 0, LOAR0
Local Output Advancement Register 1, LOAR1
Reserved
Local BER Input Selection Register, LBIS
Local BER Register, LBERR
Backplane BER Input Selection Register, BBIS
Backplane BER Register, BBERR
DPLL Operation Mode Register 1, DOM1
DPLL Operation Mode Register 2, DOM2
DPLL Output Adjustment Register, DPOA
DPLL House Keeping Register, DHKR
Zarlink Semiconductor Inc.
ZL50031
18
Location
Data Sheet