zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 34

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

20.0
The ZL50031 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the
boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
20.1
The Test Access Port (TAP) accesses the ZL50031 test functions. It consists of three input pins and one output pin
as follows:
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20.2
The ZL50031 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a four-
bit instruction register. Instructions are serially loaded into the instruction register from TDi when the TAP Controller
is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to select the
test data register that may operate while the instruction is current and to define the serial test data register path that
is used to shift data between TDi and TDo during data register scanning.
20.3
As specified in IEEE 1149.1, the ZL50031 JTAG interface contains three test data registers:
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20.4
A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on-
chip clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or
out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering
with the on-chip logic.
Test Mode Select Input (TMS) - The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDo. The data out of the
TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDO driver is set to a high impedance state.
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven
from an external source. An external pull-down resistor is required on this pin so that the ZL50031 will not enter
the JTAG test mode during power up.
The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the ZL50031 core logic.
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo.
The Device Identification Register - The JTAG device ID for the ZL50031 is 0086614B
Version<31:28>:0000
Part No. <27:12>:0000 1000 0110 0110
Manufacturer ID<11:1>: 0001 0100 101
LSB<0>:1
Test Access Port (TAP)
Instruction Register
Test Data Register
BSDL
JTAG Support
Zarlink Semiconductor Inc.
ZL50031
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Data Sheet