zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 38

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

Read/Write Addresses:
Reset Value: 0000
LIDR0 0
LIDR1 0
LIDR2 0
LIDR3 0 LID114
LIDR4 0 LID144
LIDR5 0
8-6
5-3
1-0
Bit
2
15
BBPD2-0
LBPD2-0
Unused
LID24
LID54
LID84
Name
14
BPE
0
LID113
LID143
LID23
LID53
LID83
13
0
Table 10 - Block Programming Mode (BPM) Register Bits (continued)
H
Backplane Block Programming Data Bits: These bits carry the value to be loaded into
the backplane connection memory block whenever the Memory Block Programming feature
is activated. After the MBP bit in the Control Register is set to high and the BPE is set to
high, the contents of the bits BBPD2 - 0 are loaded into bits 15 - 13 of the backplane
connection memory. Bits 12 - 0 of the backplane connection memory are programmed to be
zero.
Local Block Programming Data Bits: These bits carry the value to be loaded into the
local connection memory whenever the Memory Block Programming feature is activated.
After the MBP bit in the Control Register is set to high and the BPE is set to high, the
contents of the bits LBPD2 - 0 are loaded into bits 15 - 13 of the local connection memory.
Bits 12 - 0 of the local connection memory are programmed to be zero.
Block Programming Enable: A low to high transition of this bit enables the Memory Block
Programming function. The BPE, BBPD2-0 and LBPD2-0 in the BPM register must be
defined in the same write operation. Once the BPE bit is set to high, ZL50031 requires two
frames to complete the block programming. After the block programming has finished, the
BPE bit returns to low to indicate that the operation is complete. When BPE is high, BPE or
MBP can be set to low to abort the programming operation. When BPE is high, the other
bits in the BPM register must not be changed for two frames to ensure proper operation.
Whenever the microprocessor writes BPE to be high to start the block programming
function, the user must maintain the same logical value on the other bits in the BPM register
to avoid any change in the setting of the device.
Reserved. In normal functional mode, these bits MUST be set to zero.
LID112
LID142
LID22
LID52
LID82
12
0
0004
0006
0008
LID141
LID111
LID21
LID51
LID81
11
0
H
H
H
for LIDR0 register,
for LIDR2 register,
for LIDR4 register,
LID110
LID140
LID20
LID50
LID80
10
0
LID104
LID134
LID14
LID44
LID74
9
0
Zarlink Semiconductor Inc.
ZL50031
LID103
LID133
LID13
LID43
LID73
8
0
38
0007
0009
0005
LID102
LID132
LID12
LID42
LID72
7
0
Description
H
H
H
for LIDR1 register,
for LIDR3 register,
for LIDR5 register,
LID101
LID131
LID11
LID41
LID71
6
0
LID100
LID130
LID10
LID40
LID70
5
0
LID124
LID154
LID04
LID34
LID64
LID94
4
LID123
LID153
LID03
LID33
LID63
LID93
3
LID122
LID152
LID02
LID32
LID62
LID92
2
LID121
LID151
LID01
LID31
LID61
LID91
Data Sheet
1
LID120
LID150
LID00
LID30
LID60
LID90
0