zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 28

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

During a reference switch, the State Machine module first changes the mode of the DPLL from the Normal to the
Holdover Mode. In the Holdover Mode, the DPLL no longer uses the virtual reference signal, but generates very
accurate outputs using storage techniques.
Because the input reference coming from the Skew Control circuit is asynchronous to the sampling clock used in
the MTIE circuit, a phase error may exist between the selected input reference signal and the output signal of the
DPLL. In the worst case, the Maximum Time Interval Error (MTIE) is one period of the internally used clock cycle
(65.536 MHz if the selected reference frequency is 8 kHz, 2.048 MHz and 8.192 MHz, and 49.408 MHz when the
selected reference frequency is 1.544 MHz). This phase error is a function of the difference in phase between the
two input reference signals during reference rearrangements. Each time a reference switch is made, the delay
between the input signal and the output signal can change. The value of this delay is the accumulation of the error
measured during each reference switch. After many switches from one reference to another, the delay between the
selected input reference and the DPLL output clocks can become unacceptably large. The user should provide
MTIE reset (set MRST bit in the DOM2 register to high) causing output clocks to align to the nearest edge of the
selected input reference. It is recommended that the MTIE is reset after multiple reference switchings and the
device falls back to its initial reference. The MTIE MUST be kept in the reset mode when the ZL50031 is operating
in the slave mode.
17.3
The Phase Detector circuit compares the virtual reference signal from the MTIE Circuit with the feedback signal
from the Frequency Select MUX circuit with respect to their rising edges, and provides an error signal
corresponding to the phase difference between the two. This error signal is passed to the Phase Offset Adder
Circuit. The Frequency Select MUX allows the proper feedback signal to be selected (e.g., 8 kHz, 1.544 MHz,
2.048 MHz or 8.192 MHz).
17.4
The Phase Offset Adder Circuit adds the PHASE_OFFSET word (bits POS6-POS0 of the DPLL Output Adjustment
register - see Table 22 on page 50) to the error signal from the Phase Detector circuit to create the final phase error.
This value is passed to the Phase Slope Limiter circuit. The PHASE_OFFSET word can be positive or negative.
Since the PLL will stabilize to a situation where the average of the sum of the phase offset word and the phase
detector output is zero, a nonzero value in the input of the Phase Offset Adder circuit will result in a static phase
offset between the input and output signals of the DPLL.
Together with the Skew Control bits (SKC2-0), users can program a static phase offset between -960 ns and
+990 ns if the selected input reference of the DPLL is either 8 kHz or 2.048 MHz. If the selected reference is
1.544 MHz, the programmable phase offset is between -1.27 µs and 1.30 µs. For the programmable ranges
mentioned above, the resolution is 1.9 ns per step. See Table 22 on page 50 for the content of the DPOA register.
When the selected input reference frequency of the DPLL is 8.192 MHz (“A Clocks” or “B Clocks” are selected as
the reference), the Phase Offset Adder is bypassed. The output of the Phase Detector circuit is connected directly
to the input of the Phase Slope Limiter circuit. When an 8.192 MHz clock (C8_A_io or C8_B_io) is used as the
reference in the Secondary Master or the Slave mode, the H.110 standard requires the output clock to always
follow the input reference on an edge-to-edge basis, so the static phase offset is not required.
17.5
The limiter receives the error signal from the Phase Offset Adder circuit and ensures that the DPLL responds to all
input transient conditions with a maximum output phase slope of 7.6 ns per 125 µs. Because of this slope, the
ZL50031 is within the maximum phase slope of 81 ns per 1.326 ms specified by the Telcordia GR-1244-CORE
standard.
The frequency stability of the Holdover Mode is ±0.07 ppm, which translates to a worst case 49 frame (125 µs) slips
in 24 hours. This is better than the Telcordia GR-1244-CORE Stratum 3 requirement of ±0.37 ppm (255 frame slips
per 24 hours).
Phase Detector
Phase Offset Adder
Phase Slope Limiter
Zarlink Semiconductor Inc.
ZL50031
28
Data Sheet