zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 35

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zl50031

Manufacturer Part Number
zl50031
Description
Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
Manufacturer
Zarlink Semiconductor
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
zl50031QEG1
Manufacturer:
ZARLINK
Quantity:
431
21.0
15-14
13-12
11-10
15
0
Bit
9
8
7
6
5
4
3
Read/Write Address: 0000
Reset Value: 0000
14
0
Register Descriptions
Unused
STS3-2
STS1-0
CBERB
SBERB
CBERL
Unused
SBERL
STS3
Name
PRST
MBP
13
STS2
12
H
Reserved.
ST-BUS Frame Pulse and Clock Output Selection 1: These two bits are used to select
different frequencies for the ST-BUS output frame pulse (ST_FPo1) and clock
(ST_CKo1).
ST-BUS Frame Pulse and Clock Output Selection 0: These two bits are used to select
different frequencies for the ST-BUS output frame pulse (ST_FPo0) and clock
(ST_CKo0).
PRBS Reset: When high, the PRBS transmitter output will be initialized.
Backplane Bit Error Rate Test Clear: A low to high transition of this bit will reset the
backplane internal bit error counter and the Backplane BER register (BBERR).
Backplane Start Bit Error Rate Test: A low to high transition in this bit starts the
backplane bit error rate test. The bit error test result is kept in the Backplane BER register
(BBERR).
Local Bit Error Rate Test Clear: A low to high transition of this bit will reset the local
internal bit error counter and the Local BER register (LBERR).
Local Start Bit Error Rate Test: A low to high transition in this bit starts the local bit error
rate test. The bit error test result is kept in the Local BER register (LBERR).
Reserved. In normal functional mode, this bit MUST be set to zero.
Memory Block Programming: When this bit is high, the connection memory block
programming feature is ready for the programming of bit 13 to bit 15 of the backplane
connection memory and local connection memory. When it is low this feature is disabled.
H
STS1
11
STS3 STS2 ST_FPo1 Pulse Width
STS1 STS0 ST_FPo0 Pulse Width
STS0
0
0
1
0
0
1
10
Table 8 - Control Register (CR) Bits
PRST
0
1
0
0
1
0
9
Zarlink Semiconductor Inc.
CBEBB
ZL50031
8
244 ns
122 ns
244 ns
122 ns
61 ns
61 ns
35
SBERB
7
Description
CBERL
6
SBERL
ST_CKo1 Frequency
ST_CKo0 Frequency
5
16.384 MHz
16.384 MHz
4.096 MHz
8.192 MHz
4.096 MHz
8.192 MHz
4
0
MBP
3
MS2
2
Data Sheet
MS1
1
MS0
0

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