zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 27

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

17.0
As shown in Figure 8, "Block Diagram of the PLL Module" on page 27, the PLL module consists of a Skew Control,
Maximum Time Interval Error (MTIE), Phase Detector, Phase Offset Adder, Phase Slope Limiter, Loop Filter,
Digitally Controlled Oscillator (DCO), Divider and Frequency Select MUX modules.
17.1
The circuit delays a selected reference input with a tapped delay line with seven taps - see Figure 9, "Skew Control
Circuit Diagram" on page 27. The maximum delay of the per unit delay element is factored at intervals of 3.5 ns.
The tap is selected by the SKEW_CONTROL bus which is programmed by the SKC2-SKC0 bits of the DPLL
Output Adjustment (DPOA) register. The skew of this input will result in a static phase offset which varies from 0 to
7 steps of the maximum delay per unit delay element, between the input and the outputs of the DPLL.
17.2
The MTIE circuit prevents any significant change in the output clock phase during a reference switch. Because the
input references can have any relationship between their phases and the output follows the selected input
reference, any switch from one reference to another could cause a large phase jump in the output clock if such a
circuit did not exist. This large phase jump could cause significant data loss. The MTIE circuit keeps the phase
difference between the output clock of the DPLL and the input reference the same as if the reference switch had not
taken place.
SKEW_CONTROL
REF
Skew Control
Maximum Time Interval Error (MTIE)
Phase Locked Loop (PLL) Circuit
(Fig 18)
Control
Skew
reference
input
SKEW_CONTROL
MTIE_RESET
MTIE
REF_VIR
PHASE_OFFSET
Figure 8 - Block Diagram of the PLL Module
Figure 9 - Skew Control Circuit Diagram
Detector
Phase
FREQ_MOD
FEEDBACK
Zarlink Semiconductor Inc.
Phase
Offset
Adder
ZL50031
27
HOLDOVER_RESET
Limiter
Phase
Slope
HOLDOVER
Filter
Loop
Frequency
Select
MUX
DCO
FRAME
Divider
delayed
reference
C2M
Data Sheet
C32/64
CT_C8
C1M5o
CT_FRAME