zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 29

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

17.6
The Loop Filter circuit gives frequency offset to the DCO circuit, based on the phase difference between the input
and the feedback reference. It is similar to a first order low pass filter, with two positions for cut-off frequency (-3 dB
attenuation) depending on the selected reference frequency, and it largely determines the jitter transfer function of
the DPLL.
In Primary Master mode when the selected input reference frequency is 2.048 MHz, 1.544 MHz or 8 kHz, the cut-
off frequency is approximately at 1.52 Hz and all the reference variations, including jitter, are attenuated according
to the DPLL jitter transfer function (see Figure 10, "DPLL Jitter Transfer Function Diagram - Wide Range of
Frequencies" on page 31 and Figure 11, "Detailed DPLL Jitter Transfer Function Diagram" on page 32). The Loop
Filter circuit ensures that the jitter transfer requirements in ETS 300-011 and Telecordia GR-499-CORE are met
when the selected reference frequency is 2.048 MHz, 1.544 MHz or 8 kHz.
When the selected input reference frequency is 8.192 MHz (i.e., in Secondary Master or Slave modes), the
reference variations are bypassed to the output clocks. The cut-off frequency is at about 100 kHz, well beyond
500 Hz, the corner frequency of the Telcordia GR-1244-CORE input jitter tolerance curve.
The storage techniques, which enable generating very accurate output frequencies during the Holdover Mode of
DPLL, are built into the Loop Filter circuit. When no jitter is presented on the selected input reference, the holdover
frequency stability is 0.007 ppm.
17.7
The DCO circuit adds frequency offset from the Loop Filter (which represents the phase error between the input
and the feedback reference), to the ideal center frequency value and generates an appropriately corrected output
high speed clock.
In the Normal Mode, the DCO circuit provides an output signal which is frequency and phase locked to the selected
input reference signal.
In the Holdover Mode, the DCO circuit is running at a frequency that is equal to the frequency which was generated
by the DCO circuit when the DPLL was in the Normal Mode.
In the Freerun Mode, the DCO circuit is freerunning at its center frequency with an output accuracy equal to the
accuracy of the device master clock (C20i).
17.8
The Divider Circuit divides the DCO output frequency down to the required outputs. The following outputs are
generated:
•
•
The CT_FRAME and the CT_C8 are required clocks. C1M5o is provided as an output clock of the ZL50031.
The duty cycle of all output signals is independent of the duty cycle of the device master clock, C20i. The CT_C8,
C2M and C1M5o clocks have nominal 50% duty cycle,
The output frame pulse (CT_FRAME) is generated in such a way that it is always aligned with the CT_C8 clock to
form the required H.110 CT Bus clock and frame pulse shape (when the CT_FRAME is low the rising edge of the
CT_C8 defines the frame boundary). Depending on the selected input reference frequency, the CT_FRAME is
generated in the following way:
•
C64 (65.536 MHz clock) - used as the internal clock for the ZL50031 device.
CT_C8 (8.192 MHz clock), C2M (2.048 MHz clock), C1M5o (1.544 MHz clock) and CT_FRAME (8 kHz
negative frame pulse) - feedback reference signals to the Frequency Select MUX Circuit.
When the input reference frequency is 8 kHz, the output frame pulse is aligned with the rising edge of the
reference.
Loop Filter
Digitally Controlled Oscillator (DCO)
Divider
Zarlink Semiconductor Inc.
ZL50031
29
Data Sheet