zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 16

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

8.0
The ZL50031 block programming mode (BPM) register provides users with the capability of initializing the local and
backplane connection memories in two frames. Bit 13 - bit 15 of every backplane connection memory location will
be programmed with the pattern stored in bit 6 - bit 8 of the BPM register. Bit 13 - bit 15 of every local connection
memory location will be programmed with the pattern stored in bits 3 to 5 of the BPM register. The other bit
positions of the backplane connection memory and the local connection memory are loaded with zeros. See Figure
4 on page 16 for the connection memory contents when the device is in block programming mode.
The block programming mode is enabled by setting the memory block program (MBP) bit of the Control Register to
high. After the block programming enable (BPE) bit of the BPM register is set to high, the block programming data
will be loaded into bits 13 to 15 of every backplane connection memory location and bits 13 to 15 of every local
connection memory low location. The other connection memory bits are loaded with zeros. When the memory block
programming is completed, the device resets the BPE bit to low. See Table 10 on page 37 for the bit assignment of
the BPM register.
9.0
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform time slot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications it is recommended to select variable throughput delay to
ensure minimum delay between input and output data. In wideband data applications it is recommended to select
constant throughput delay to maintain the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected in the BTM2 - BTM0 bits of
the backplane connection memory or LTM0 - LTM2 bits of the local connection memory as described in Table 24 on
page 51 and Table 27 on page 53, respectively.
9.1
The delay in this mode is dependent only on the combination of source and destination channels and is
independent of input and output streams. The minimum delays achievable in the ZL50031 device are 3-channel
delay, 5-channel delay, and 10-channel delay for the 2 Mbps, 4 Mbps, and 8 Mbps data rates respectively. The
maximum delay is one frame plus 3 channels, one frame plus 5 channels, and one frame plus 10 channels for the
2 Mbps, 4 Mbps and 8 Mbps modes respectively.
For the backplane interface, the variable delay mode can be programmed through the backplane connection
memory bits, BTM2 - BTM0. When BTM2 - BTM0 are programmed to “000”, it is a per-channel variable delay from
local input to the backplane output. When BTM2 - BTM0 are set to “010”, it is a per-channel variable delay from
backplane input to backplane output.
BBPD2
Variable Delay Mode
LBPD2
Memory Block Programming
Delay Through the ZL50031
15
15
BBPD1
LBPD1 LBPD0
14
14
BBPD0
13
13
Figure 4 - Block Programming Data in the Connection Memories
0
12
12
0
11
11
0
0
Backplane Connection Memory (BCM)
Local Connection Memory (LCM)
10
10
0
0
Zarlink Semiconductor Inc.
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9
0
0
ZL50031
8
8
0
0
16
7
7
0
0
6
6
0
0
5
5
0
0
4
4
0
0
3
3
0
0
2
2
0
0
1
1
0
0
Data Sheet
0
0
0
0