zl50031 Zarlink Semiconductor, zl50031 Datasheet - Page 30

• Manufacturer Part Number: zl50031
• Description: Flexible 4 K X 2 K Channel Digital Switch With H.110 Interface And 2 K X 2 K Local Switch
• Manufacturer: Zarlink Semiconductor

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17.9
According to the selected input reference of the DPLL, this MUX will select the appropriate output frequency to be
the feedback signal to the PLL and MTIE Circuits.
18.0
The following are some the DPLL performance indicators and their corresponding definitions.
18.1
Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may
also be measured when the device is in a non-synchronizing mode, such as freerun or holdover, by measuring the
output jitter of the device. Intrinsic jitter is usually measured with various band-limiting filters depending on the
applicable standards. See “AC Electrical Characteristics†- Output Clock Jitter Generation (Unfiltered)” on page 64
for jitter values.
18.2
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e., remain in lock and
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depend on the applicable standards. The input jitter
tolerance of the DPLL depends on the selected reference frequency and can not exceed: ±15 U.I. for E1 or T1
references, and ±1 U.I. for 8 kHz references.
18.3
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
In slave and secondary master mode the H.110 standard requires the “B Clocks” to be edge-synchronous with the
“A Clocks”, as long as jitter on the “A Clocks” meets Telcordia GR-1244-CORE specifications. Therefore in these
two modes no jitter attenuation is performed.
In primary master mode the jitter attenuation of the DPLL is determined by the internal 1.52 Hz low pass Loop Filter
and the Phase Slope Limiter. Figure 10, "DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies" on
page 31 shows the DPLL jitter transfer function diagram in a wide range of frequencies, while Figure 11, "Detailed
DPLL Jitter Transfer Function Diagram" on page 32 is the portion of the diagram from Figure 10 around 0 dB of the
jitter transfer amplitude. At this point it is possible to see that when operating in primary master mode the DPLL is a
second order, type 2 PLL. The jitter transfer function can be described as a low pass filter to 1.52 Hz -
20 dB/decade, with peaking less then 0.5 dB.
When the reference frequency is either 2.048 MHz or 1.544 MHz, the CT_FRAME randomly defines the
output frame boundary, always keeping the described relation to the CT_C8 clock.
When the reference frequency is 8.192 MHz, the output frame pulse (CT_FRAME) has to be aligned with the
input frame pulse (FRAME_A_io or FRAME_B_io). Since an 8.192 MHz clock (either C8_A_io or C8_B_io)
is used as the reference clock, the selected frame pulse from the Frame Select MUX is provided as the input
to the Divider circuit and the CT_FRAME is synchronized to it.
Frequency Select MUX Circuit
Intrinsic Output Jitter
Jitter Tolerance
Jitter Transfer
Measures of Performance
Zarlink Semiconductor Inc.
ZL50031
30
Data Sheet