bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 83

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

Bt8970
Single-Chip HDSL Transceiver
Table 5-14. Microcomputer Interface Switching Characteristics
100101B
NOTE(S):
1. Read Strobe is defined as RD and CS asserted in Intel mode, and DS and CS asserted when R/W is high in Motorola mode.
1. When writing an interrupt mask or status register.
2. Write Strobe is defined as WR and CS asserted in Intel mode, and DS and CS asserted when R/W is low in Motorola mode.
3. Writes to internal registers are synchronized to an internal 64-times symbol-rate clock. Data is available for reading after the
4. When performing an indirect write to RAM-based locations using a write select register [odd addresses: 0x71–0x7B] and the
5. When performing an indirect read from RAM-based locations using a read select register [even addresses: 0x70–0x7A] and the
6. The timing listed is for the synchronous mode of the MCI. It can also be set to asynchronous mode by setting bit 0 of the
Symbol
specified time. This parameter may extend the overall read access time from internal register locations under high bus
speed/low symbol rate conditions.
Access Data Register. Subsequent writes to any read/write select register or the Access Data Register, as initiated by a Write
Strobe falling edge, is prohibited for the specified time. This parameter will extend the overall write access time to RAM-based
locations under normal bus speed/symbol rate conditions.
Access Data Register. Subsequent writes to any read/write select register, as initiated by a Write Strobe falling-edge, is
prohibited for the specified time. Data is available for reading from the Access Data Register after the specified time. This
parameter will extend the overall read access time from RAM-based locations under normal bus speed/symbol rate conditions.
Direct writes to the Access Data Register are as specified for internal registers.
reserved2 register (address 0x0F) to a 1. In this case the minimum timing changes to 40 us for symbol 39, and 50 ns for
symbols 40 and 50. Synchronous mode is preferred because it reduces internal switching noise, however no significant
performance degradation has been measured as a result of using the asynchronous mode.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Data Out Enable (Low Z) after Read Strobe Falling Edge
Data Out Valid after Read Strobe Low
Data Out Hold after Read Strobe Rising Edge
Data Out Disable (High Z) after Read Strobe High
IRQ Hold after Write Strobe Rising Edge
IRQ Delay after Write Strobe High
Internal Register Delay after Write Strobe High
Internal RAM Delay after Write Strobe High
Access Data Register Delay after Write Strobe High
READY Falling Edge after Write Strobe Low
READY Rising Edge after Write Strobe High
READY Falling Edge after Read Strobe Low
READY Rising Edge after Read Strobe High
Data Out Valid after READY low
Preliminary Information/Conexant Proprietary and Confidential
Parameter
(2,3)
(1, 7)
(2,3)
(1)
(3,5)
(3)
(1)
(3)
(1)
(3,4)
Conexant
(1)
(3,6)
(1)
5.0 Electrical & Mechanical Specifications
Minimum
—
—
—
—
—
—
—
2
2
5
0
0
0
0
5.6 Microcomputer Interface Timing
0.5* Tmclk +25
Tqclk ÷ 32 + 20
0.5*Tmclk +25
0.5*Tmclk +25
Maximum
Tqclk ÷ 32
2* Tqclk
2*Tqclk
—
—
25
—
50
50
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5-11