bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 69

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

Bt8970
Single-Chip HDSL Transceiver
0x76—Scratch Pad Read Tap Select (sp_tap_select_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals.
When written, it causes the selected 8-bit scratch pad memory location to be subsequently loaded into the
lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within two symbol periods.
Does not affect the value of the memory. No other data access may occur between the time the Read Tap Select
Register is written and the time the Access Data Register is read or the data may be corrupted.
0x77—Scratch Pad Write Tap Select (sp_tap_select_write)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 63 decimals.
When written, it causes the lowest-order 8 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F]
to be subsequently written to the selected scratch pad memory location within two symbol periods. Does not
affect the value of the access data register.
0x78—Equalizer Read Select Register (eq_add_read)
A 6-bit read/write register representing an unsigned binary address defined over a range of 0 to 47 decimals.
When written, it causes the selected 16-bit location of the equalizer register file to be subsequently loaded into
the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within two symbol
periods. Does not affect the value of the register file location. An address map of the shared register file, as
defined by the factory-delivered microcode, is shown below. No other data access may occur between the time
the Read Tap Select Register is written and the time the Access Data Register is read or the data may be
corrupted.
100101B
7
–
7
–
7
–
6
6
6
–
–
–
Preliminary Information/Conexant Proprietary and Confidential
D[5]
D[5]
D[5]
5
5
5
D[4]
D[4]
D[4]
4
4
4
Conexant
D[3]
D[3]
D[3]
3
3
3
D[2]
D[2]
D[2]
2
2
2
D[1]
D[1]
D[1]
1
1
1
4.0 Register
D[0]
D[0]
D[0]
0
0
0
4-25