bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 79

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

Bt8970
Single-Chip HDSL Transceiver
Table 5-9. Channel-Unit Interface Timing Requirements, Parallel Slave Mode
Table 5-10. Channel Unit Interface Switching Characteristics, Parallel Slave Mode
100101B
NOTE(S):
(1)
(2)
NOTE(S):
1. RBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes; 0x06].
Symbol
Symbol
18
19
20
21
22
TBCLK and RBCLK must be frequency locked to QCLK though they may have independent phase relationships to QCLK and to
one another.
TBCLK polarity (edge sensitivity) is programmable through the CU Interface Modes Register [cu_interface_modes 0x06].
23
24
TBCLK, RBCLK Period
TBCLK
TBCLK
TQ[1,0] Setup prior to TBCLK Active Edge
TQ[1,0] Hold after TBCLK High/Low
RQ[1,0] Hold after RBCLK Active Edge
RQ[1,0] Delay after RBCLK High/Low
,
,
RBCLK Pulse-Width High
RBCLK Pulse-Width Low
Preliminary Information/Conexant Proprietary and Confidential
(1)
Parameter
Parameter
(2)
(1)
(1)
(2)
Conexant
5.0 Electrical & Mechanical Specifications
Minimum
Minimum
T
T
QCLK
QCLK
5.5 Channel Unit Interface Timing
T
QCLK
25
25
—
0
4
4
Maximum
Maximum
T
100
QCLK
—
—
—
—
—
Units
Units
—
—
—
ns
ns
ns
ns
5-7