bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 61

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

Bt8970
Single-Chip HDSL Transceiver
0x36, 0x37—Cursor Level Register (cursor_level_low, cursor_level_high)
A 2-byte read/write register interpreted as a 16-bit, 2’s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x2AAA (one-third of the maximum positive value). The value
of this register represents the expected level of a noise-free +1 receive symbol at the output of the DFE. It is
multiplied by 2 to produce the positive and negative slicing levels, in addition to zero, used by the symbol
detector in four-level slicing mode. This value is also used to scale the detector output when computing the
equalizer error and slicer error signals. The detected symbol (–3, –1, +1, +3) is multiplied by the value of this
register to produce the scaled output.
0x38, 0x39—DAGC Target Register (dagc_target_low, dagc_target_high)
A 2-byte read/write register interpreted as a 16-bit, 2’s-complement number. The range of meaningful values is
limited to positive integers between 0x0000 and 0x7FFF. The value of this register is subtracted from the
absolute value of the receive signal at the output of the Digital Automatic Gain Control (DAGC) function. The
difference is used as the error input to the DAGC while in the self-adaptation mode. In the DAGC’s
equalizer-error adaptation mode, the contents of this register are not used.
0x3A—Symbol Detector Modes Register (detector_modes)
enable_peak_
detector
output_mux_
control[1,0]
scr_out_to_dfe
100101B
enable_peak_det
ector
7
output_mux_con
Enable Peak Detector—Read/write control bit that enables the peak detection function when
set; disables the function when cleared. When enabled, the peak detector output overrides the
slicer output if the peak detection criteria are met. If the criteria are not met, or if the function
is disabled, the slicer output is used and peak detector output is ignored.
Output Multiplexer Control—Read/write binary field that selects the source of the detector
output connected to the channel unit receive interface.
Scrambler Output to DFE—Read/write control bit that selects the source of the detector output
connected to the DFE and timing recovery module inputs, and the transmitter’s detector
loopback input. When set, this bit selects the scrambler/descrambler function; when cleared, it
selects the slicer/peak detector output.
trol[1]
6
Preliminary Information/Conexant Proprietary and Confidential
output_mux_control[1,0]
output_mux_con
trol[0]
5
00
01
10
11
scr_out_to_dfe
4
Conexant
two_level
Transmitter loopback output from CU transmit interface
3
Detector Output to CU Receive Interface
Same as scr_out_to_dfe selection
Scrambler/descrambler output
lfsr_lock
2
Reserved
htur_lfsr
1
4.0 Register
descr_on
0
4-17