bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 37

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

Bt8970
Single-Chip HDSL Transceiver
2.6 Test and Diagnostic Interface (JTAG)
As the complexity of communications chips increases, the need to easily access individual chips for PCB
verification is becoming vital. As a result, special circuitry has been incorporated within the transceiver which
complies fully with IEEE standard 1149.1-1990, “Standard Test Access Port and Boundary Scan Architecture”
set by the Joint Test Action Group (JTAG).
Clock (TCK), Test Data Input (TDI), and Test Data Out (TDO). Verification of the integrated circuit and its
connection to other modules on the printed circuit board can be achieved through these four TAP pins.
outputs. All scan cells are interconnected into a boundary-scan register which applies or captures test data used
for functional verification of the PC board interconnection. JTAG is particularly useful for board testers using
functional testing methods.
provided. Since all of the digital pins are interconnected as a long shift register, the TAP logic has access and
control of all necessary pins to verify functionality. For mixed signal ICs, the chip boundary definition is
expanded to include the on-chip interface between digital and analog circuitry. Internal supply monitor circuitry
ensures that each pin is initialized to operate as an 2B1Q transceiver, instead of JTAG test mode during a
powerup sequence.
revision number, a part number, and a manufacturers identification code specific to Rockwell. Access to this
register is through the TAP controller via the standard JTAG instruction set (see
verified at all digital pins through a set of four instructions accessible through the use of a state machine
standard to all JTAG controllers. Refer to the IEEE 1149.1 specification for details concerning the Instruction
Register and JTAG state machine. A Boundary Scan Description Language (BSDL) file for the Bt8970 is also
available from the factory upon request.
Table 2-8. JTAG Device Identification Register
100101B
0
(1)
Version
JTAG has four dedicated pins that comprise the Test Access Port (TAP): Test Mode Select (TMS), Test
JTAG’s approach to testability utilizes boundary scan cells placed at each digital pin, both inputs and
With boundary-scan cells at each digital pin, the ability to apply and capture the respective logic levels is
The JTAG standard defines an optional device identification register. This register is included and contains a
A variety of verification procedures can be performed through the TAP controller. Board connectivity can be
4 bits
Consult factory for current version number
0x0
0
0
(1)
0
0 0 1 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1
Preliminary Information/Conexant Proprietary and Confidential
0x230A (Bt8970)
Part Number
16 bits
Conexant
Manufacturer ID
2.6 Test and Diagnostic Interface (JTAG)
Table
11 bits
0x0D6
2.0 Functional Description
2-8).
1
0
1
TDO
2-19