bt8970 Mindspeed Technologies, bt8970 Datasheet
bt8970
Available stocks
Related parts for bt8970
bt8970 Summary of contents
Page 1
... The Bt8970 is a highly integrated device that includes all of the active circuitry needed for a complete 2B1Q transceiver. In the receive portion of the Bt8970, a variable gain amplifier optimizes the signal level according to the dynamic range of the analog-to-digital converter. Once the signal is digitized, sophisticated adaptive echo cancellation, equaliza- tion, and detection DSP algorithms reproduce the originally transmitted far-end signal ...
Page 2
... Ordering Information Model Number Bt8970EHF 100-Pin Plastic Quad Flat Pack Revision History Revision Level A Advance B — © 1997, 2000, Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials ...
Page 3
Table of Contents List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
... Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.4 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.5 Channel Unit Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Microcomputer Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.6 Test and Diagnostic Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.6.1 Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.6.2 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.6.3 5.7 Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.8 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 iv Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Conexant Bt8970 100101B ...
Page 5
... Single-Chip HDSL Transceiver List of Figures Figure 1-1. HDSL T1/E1 Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Figure 1-2. Bt8970 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Figure 1-3. Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Figure 2-1. Transmit Section Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Figure 2-2 ...
Page 6
... List of Figures vi Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver Conexant Bt8970 100101B ...
Page 7
... Bt8970 Single-Chip HDSL Transceiver List of Tables Table 1-1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Table 1-2. Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Table 2-1. Symbol Source Selector/Scrambler Modes 2-2 Table 2-2. Four-Level Bit-to-Symbol Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Table 2-3 ...
Page 8
... List of Tables viii Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver Conexant Bt8970 100101B ...
Page 9
... Only) E1 Framer Transmit Line The Bt8970 comprises five major functions: a transmit section, a receive section, a timing recovery and clock interface, a microcomputer interface, and a test and diagnostic interface. connections within and between each of these functional blocks. 100101B Preliminary Information/Conexant Proprietary and Confidential 1-1 ...
Page 10
... System Overview 1.1 Functional Summary Figure 1-2. Bt8970 Detailed Block Diagram Receive Section RXP RXN ADC VGA RXBP RXBN Microcomputer Interface and System Control AD[7:0] ADDR[7:0] MUXED MOTEL WR/R/W Microcomputer Interface RD/DS CS ALE RST READY IRQ Transmit Section TXP Line Driver TXN TXLDIN TXPSN TXLDIP TXPSP ...
Page 11
... Analog-to-Digital Converter (ADC) can be maximized according to the attenuation of the subscriber line. Digitized receive data is passed to the Digital Signal Processor (DSP) portion of the Bt8970. After DC offset cancellation, a replica of the transmit signal is subtracted from the total receive signal by a digital echo canceller ...
Page 12
... The serial monitor output can be viewed as a real-time virtual probe for looking at the transceiver’s internal signals. The programmable signal source is shifted out serially at 16 times the symbol rate. The majority of the receive signal path is accessible through this output. 1-4 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver Conexant Bt8970 100101B ...
Page 13
... Bt8970 Single-Chip HDSL Transceiver 1.2 Pin Descriptions The Bt8970 is packaged in a 100-Pin Plastic Quad Flat Pack (PQFP). The pin assignments are shown in Figure 1-3. A listing of pin labels, numbers, and I/O assignments is given in provided in Table 1-2. The coding used in the I/O column is digital output analog output open-drain output digital input analog input, and I/O = bidirectional ...
Page 14
... DTEST2 I 69 TXLDIP DTEST3 I 70 TXLDIN VPLL – 71 TXP PGND – 72 VAA DTEST4 I 73 AGND AGND – 74 TXN AGND – 75 AGND Conexant Bt8970 Single-Chip HDSL Transceiver I/ I/O Pin Pin Label AGND – RXP IA – 78 RXN IA – 79 RXBP IA – 80 RXBN VAA – ...
Page 15
... Bt8970 Single-Chip HDSL Transceiver Table 1-2. Hardware Signal Definitions ( Pin Label Signal Name I/O MOTEL Motorola/Intel ALE Address Latch Enable CS Chip Select RD/DS Read/Data Strobe WR / R/W Write/ Read/Write AD[7:0] Address-Data[7:0 I/O ] ADDR[7:0] Address Bus (not multiplexed)[7:0] MUXED Addressing Mode Select READY Ready OD IRQ Interrupt Request OD RST ...
Page 16
... unused, it should be tied to VDD2 or DGND. I Functions as the receive baud-rate clock input. It must be frequency locked to QCLK. This input is used only when the channel unit interface is in parallel slave mode unused, it should be tied to VDD2 or DGND. Conexant Bt8970 Single-Chip HDSL Transceiver 100101B ...
Page 17
... Connection point for the crystal. HCLK can be configured to run at 16, 32 times the symbol rate. Upon reset set to 16 times the symbol rate. This clock will be phase locked to the incoming data when the Bt8970 is configured as the remote unit. Buffered-crystal oscillator output. Conexant 1 ...
Page 18
... Dedicated ground pins for the digital circuitry. Must be held at same potential as AGND and PGND. Dedicated supply pins powering the analog circuitry. Dedicated ground pins for the analog circuitry. Must be held at the same poten- tial as DGND and PGND. Conexant Bt8970 Single-Chip HDSL Transceiver 100101B ...
Page 19
Functional Description 2.1 Transmit Section The transmit section is illustrated in Figure selector/scrambler, a variable gain digital-to-analog converter (DAC), a pulse-shaping filter, and a line driver. Figure 2-1. Transmit Section Block Diagram Transmit Channel Unit TQ[1,0] Interface Isolated ...
Page 20
... Preliminary Information/Conexant Proprietary and Confidential Symbol Source Selector/Scrambler Mode Second Input Bit (magnitude Second Input Bit (magnitude) don’t care don’t care Conexant Bt8970 Single-Chip HDSL Transceiver Table 2-2. Output Symbol –3 – Output Symbol –3 +3 100101B ...
Page 21
... The Transmitter Modes Register can also be used to zero the output of the transmitter using the transmitter_off control bit. The Bt8970 can generate isolated pulses to support the testing of pulse templates. When in the isolated pulse mode, the output consists of a single pulse surrounded by zeros. ...
Page 22
... Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver RXP + Anti-alias Filter RXN – TXP Line + – TXN Driver RXBP + + Anti-alias Hybrid Filter RXBN – – Off-Chip Circuitry On-Chip Circuitry Conexant Bt8970 To ADC + – Gain[2:0] 100101_006 100101B ...
Page 23
... Bt8970 Single-Chip HDSL Transceiver 2.2.3 Digital Signal Processor The Digital Signal Processor (DSP) includes five Least Mean Squared (LMS) filters: an Echo Canceller (EC), a Digital Automatic Gain Controller (DAGC), a Feed Forward Equalizer (FFE), an Error Predictor (EP), and a Decision Feedback Equalizer (DFE). These filters are used to equalize the received signal so that the symbols transmitted from the far-end can be reliably recovered ...
Page 24
... MCI Comparator Comparator Low Threshold from MCI Far-End Alarms Absolute Accumulator Value Result Accumulator Register Result Register DC Level Signal Level Meter Meter Counter Result Register Conexant Bt8970 Single-Chip HDSL Transceiver summarizes the features high_felm Interrupt low_felm Interrupt 100101_008 100101B ...
Page 25
... Bt8970 Single-Chip HDSL Transceiver 2.2.3.2 Offset Adjustment A nonzero DC level on the input can be corrected offset value [dc_offset_low, dc_offset_high; 0x26, 0x27] which is subtracted from the input. The DC offset is a 16-bit number and is programmed via the microcomputer interface. 2.2.3.3 DC Level Meter The DC level meter provides the monitoring needed for adaptive offset compensation. The offset-adjusted input signal is accumulated over the meter timer interval [meter_low, meter_high ...
Page 26
... A zero filter output mode exists to zero the output of the FIR with no effect on the coefficients also enabled through the microcomputer interface. Individual DFE coefficients can be read and written through the microcomputer interface. Adaptation should be frozen prior to reading or writing coefficients. 2-8 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver Figure Conexant Bt8970 2-3. 100101B ...
Page 27
... Bt8970 Single-Chip HDSL Transceiver 2.2.5.5 Microcoding The DAGC, FFE, and EP filters are implemented using an internal microprogrammable Digital Signal Processor (DSP) optimized for LMS filters. Internal DSP micro-instructions are stored in an on-chip RAM. This microcode RAM is loaded after powerup through the microcomputer interface when the transceiver is initialized ...
Page 28
... At the end of the measurement interval, the 8 MSBs of the counter are loaded into the Symbol Histogram Meter Register [symbol_histogram; 0x4E]. 2-10 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver Table 2-5 for the four-level case. First Output Bit Second Output Bit (magnitude) (sign Conexant Bt8970 100101B ...
Page 29
... Bt8970 Single-Chip HDSL Transceiver The noise level meter estimates the noise at the input to the slicer. It operates by accumulating the absolute value of the slicer error over meter timer interval [meter_low, meter_high; 0x18, 0x19]. At the end of the measurement interval, the 16 MSBs of the 32-bit accumulator are loaded into the Noise Level Histogram Meter Register [nlm_low, nlm_high ...
Page 30
... Figure 2-5. Timing Recovery and Clock Interface Block Diagram Detected Symbol Equalizer Error 2-12 Preliminary Information/Conexant Proprietary and Confidential Phase Detector Control Meter Register Registers [0x40, 0x41] QCLK (87) Timing Recovery Circuit HCLK (35) XOUT (36) Crystal Ampli er XTALI (40) XTALO (39) Y1 C10 C11 Digital Ground Conexant Bt8970 Single-Chip HDSL Transceiver 100101_009 100101B ...
Page 31
... Frequency Register [pll_frequency_low, pll_frequency_high; 0x5E, 0x5F]. 2.3.0.8 Crystal Amplifier The crystal amplifier reduces the support circuitry needed for the Bt8970 by eliminating the need for an external Voltage-Controlled Crystal Oscillator (VCXO Crystal Oscillator (XO). A crystal can be connected directly to the XTALI and XTALO pins. ...
Page 32
... This clock and data relationship is illustrated in Figure 2-7. Parallel Master Mode QCLK RQ[1]/TQ[1] RQ[0]/TQ[0] 2-14 Preliminary Information/Conexant Proprietary and Confidential Magnitude Sign Magnitude Magnitude Sign Magnitude Figure 2-7. Sign Sign 1 0 Magnitude Magnitude 0 1 Conexant Bt8970 Single-Chip HDSL Transceiver Figure 2-6. Sign 2 Sign 2 100101_010 Sign 2 Magnitude 2 100101_011 100101B ...
Page 33
... Bt8970 Single-Chip HDSL Transceiver Parallel slave mode uses RBCLK and TBCLK inputs to synchronize data transfer. RBCLK and TBCLK must be frequency-locked to QCLK, though the use of two internal FIFOs allow an arbitrary phase relationship to QCLK. TQ[1] and TQ[0] are sampled on the active edge of TBCLK, as programmed through the MCI. RQ[1] and RQ[0] are output on the active edge of RBCLK, also as programmed through the MCI ...
Page 34
... AD[7:0] pins. MUXED low configures the interface to use separate address and data bused with the data on the AD[7:0] pins and the address on the ADDR[7:0] pins. The READY pin is provided to indicate when the Bt8970 is ready to transfer data and can be used by the microcomputer to insert wait states in read or write cycles. ...
Page 35
... Timers Eight timers are integrated into the Bt8970 to control the various on-chip meters and to aid the microcomputer in stepping through the events of the startup sequence. The structure of each timer includes down counter, zero detect logic, and control circuitry, which determines when the counter is reloaded or decremented ...
Page 36
... Symbol rate 1024 Startup Events Symbol rate 1024 Startup Events Symbol rate 1024 SNR Measurement Symbol rate Measurement Symbol rate Miscellaneous Symbol rate Miscellaneous Symbol rate Conexant Bt8970 Single-Chip HDSL Transceiver Control Bits sut 1 sut 2 sut 3 sut 4 snr meter t3 t4 100101B ...
Page 37
... JTAG controllers. Refer to the IEEE 1149.1 specification for details concerning the Instruction Register and JTAG state machine. A Boundary Scan Description Language (BSDL) file for the Bt8970 is also available from the factory upon request. ...
Page 38
... Functional Description 2.6 Test and Diagnostic Interface (JTAG) 2-20 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver Conexant Bt8970 100101B ...
Page 39
Register Summary Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 7 0x00 global_modes R/W hw_revision[3] 0x01 serial_monitor_source R/W hclk_freq[1] 0x02 mask_low_reg R/W t4 0x03 mask_high_reg R/W — 0x04 timer_source R/W t4 0x05 irq_source ...
Page 40
Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 7 0x12 sut2_low R/W D[7] 0x13 sut2_high R/W D[15] 0x14 sut3_low R/W D[7] 0x15 sut3_high R/W D[15] 0x16 sut4_low R/W D[7] 0x17 sut4_high R/W D[15] 0x18 meter_low ...
Page 41
Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 7 0x26 dc_offset_low R/W D[7] 0x27 dc_offset_high R/W D[15] 0x28 tx_calibrate R/W — 0x29 tx_gain R/W — 0x2A noise_histogram_th_low R/W D[7] 0x2B noise_histogram_th_high R/W D[15] 0x2C ep_pause_th_low ...
Page 42
Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 7 0x3B peak_detector_delay R/W — 0x3C dagc_modes R/W — 0x3D ffe_modes R/W — 0x3E ep_modes R/W — 0x40 pdm_low R/W D[17] 0x41 pdm_high R/W D[25] 0x42 overflow_meter ...
Page 43
Table 3-1. Register Table ( ADDR Register Read (hex) Label Write 7 0x5E pll_frequency_low R/W D[22] 0x5F pll_frequency_high R/W D[30] 0x70 linear_ec_tap_select_read R/W — 0x71 linear_ec_tap_select_write R/W — 0x72 nonlinear_ec_tap_select_read R/W — 0x73 nonlinear_ec_tap_select_write R/W — 0x74 dfe_tap_select_read ...
Page 44
... Register Summary 3-6 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver Conexant Bt8970 100101B ...
Page 45
... The zero value represents the original prototype release. Consult factory for current values and revision. Part ID—Read-only binary field set to binary 010 identifying the part as Bt8970. part_id[2:0] Power Down Mode—Read/write control bit. When set, stops all filter processing and zeros the mode transmit output for reduced power consumption ...
Page 46
... Digital Front-End Output/LEC Input Linear Echo Replica DFE Subtractor Output/EP Input EP Subtractor Output/Slicer Input Timing Recovery Phase Detector Output/Loop Filter Input Timing Recovery Loop Filter Output/Frequency Synthesizer Input 4 3 meter su4 sut3 Conexant Bt8970 Single-Chip HDSL Transceiver sut2 sut1 100101B ...
Page 47
... Bt8970 Single-Chip HDSL Transceiver 0x03—Interrupt Mask Register High (mask_high_reg) Independent read/write mask bits for each of the IRQ Source Register [irq_source; 0x05] interrupt flags. Individual mask bit behavior is identical to that specified for Interrupt Mask Register Low [mask_low_reg; 0x02 – – ...
Page 48
... Signal-to-Noise Ratio Low Alarm—Active when the SNR Alarm meter value exceeds (greater low_snr than) the threshold stored in the SNR Alarm Threshold Registers [snr_alarm_th_low, snr_alarm_th_high; 0x34–0x35]. 4-4 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver – sync high_felm Conexant Bt8970 1 0 low_felm low_snr 100101B ...
Page 49
... Bt8970 Single-Chip HDSL Transceiver 0x06—Channel Unit Interface Modes Register (cu_interface_modes – – – Transmit Baud Clock Polarity—Read/write control bit defines the polarity of the TBCLK tbclk_pol input while in the parallel slave interface mode. When set, TQ[1,0] is sampled on the falling edge of TBCLK; when cleared, TQ[1,0] is sampled on the rising edge. ...
Page 50
... Adaptation Gain—Read/write binary field which specifies the adaptation gain. adapt_gain[1,0] adapt_gain[1,0] 4-6 Preliminary Information/Conexant Proprietary and Confidential 4 3 – rphs[3] rphs[ adapt_ zero_coefficients zero_output coefficients Conexant Bt8970 Single-Chip HDSL Transceiver rphs[1] rphs[ adapt_gain[1] adapt_gain[0] Normalized Gain 512 100101B ...
Page 51
... Bt8970 Single-Chip HDSL Transceiver 0x09—Nonlinear Echo Canceller Modes Register (nonlinear_ec_modes negate_symbol symbol_delay[2] symbol_delay[1] symbol_delay[0] Negate Symbol—Read/write control bit which, when set, inverts (2’s complement) the receive negate_symbol signal path at the output of the nonlinear echo canceller. When cleared, the signal path is unaffected. This function is independent of all other NEC mode settings. Symbol Delay— ...
Page 52
... Valid output levels limited to +3, –3. 4-8 Preliminary Information/Conexant Proprietary and Confidential 4 3 transmitter_off htur_lfsr data_source[ –23 – 1); when cleared, it selects the local unit (HTU-C/LTU) –5 + 1). Transmitter Mode Conexant Bt8970 Single-Chip HDSL Transceiver data_source[1] data_source[0] Output Pulse Level –3 – 100101B ...
Page 53
... Bt8970 Single-Chip HDSL Transceiver 0x0C—Timer Restart Register (timer_restart) Independent read/write restart bits, one for each of the eight internal timers. Setting an individual bit causes the associated timer to be reloaded with the contents of its interval register. For the four symbol-rate timers (meter, snr, t3, t4), reloading will occur within one symbol period. For the four start-up timers (sut1– ...
Page 54
... Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver meter sut4 sut3 meter sut4 sut3 Conexant Bt8970 1 0 sut2 sut1 1 0 sut2 sut1 100101B ...
Page 55
... Bt8970 Single-Chip HDSL Transceiver 0x12, 0x13—Startup Timer 2 Interval Register (sut2_low, sut2_high) A 2-byte read/write register stores the countdown interval for Startup Timer 2 in unsigned binary format. Each increment represents 1,024 symbol periods. The contents of this register are automatically loaded into its associated timer after the timer’ ...
Page 56
... Preliminary Information/Conexant Proprietary and Confidential loop_back[0] – gain[2] Function Normal Operation (Loopback Disabled) Hybrid Inputs Disabled (RXBP, RXBN) Transmitting Loopback Silent Loopback VGA Gain Conexant Bt8970 Single-Chip HDSL Transceiver 1 0 gain[1] gain[0] 0dB ...
Page 57
... Clock Frequency Select—Read/write binary field specifies one of four data rate ranges for clk_freq[1,0] Bt8970 operation. The “00” state is automatically selected by RST assertion and upon initial power application. The crystal or external clock frequency must be equal to 8 times the data rate. ...
Page 58
... The value of the Transmit Calibration Register is set during manufacturing testing by Rockwell and corresponds to the value required to operate the Bt8970 at a nominal 13.5 dBm transmit power, assuming the recommended transformer coupling/hybrid circuit is used. Users may override this calibration by writing their own value into the Transmitter Gain Register [tx_gain ...
Page 59
... Bt8970 Single-Chip HDSL Transceiver 0x29—Transmitter Gain Register (tx_gain – – tx_gain[3] Transmit Gain—A 4-bit, 2’s-complement, read/write field controlling the transmitter gain. tx_gain[3:0] Upon initialization, the value in the Transmitter Calibration Register [tx_calibrate; 0x28] may be written into this register by software to set the transmitter gain to the nominal value, or the user may set it to another desired value ...
Page 60
... The value of this register is compared to the value of the SNR alarm meter. If the meter reading exceeds (greater than) this threshold, the low_snr interrupt flag is set in the IRQ Source Register [irq_source; 0x05]. 4-16 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver D[4] D[3] D[2] Conexant Bt8970 1 0 D[1] D[0] 100101B ...
Page 61
... Bt8970 Single-Chip HDSL Transceiver 0x36, 0x37—Cursor Level Register (cursor_level_low, cursor_level_high) A 2-byte read/write register interpreted as a 16-bit, 2’s-complement number. The range of meaningful values is limited to positive integers between 0x0000 and 0x2AAA (one-third of the maximum positive value). The value of this register represents the expected level of a noise-free +1 receive symbol at the output of the DFE multiplied produce the positive and negative slicing levels, in addition to zero, used by the symbol detector in four-level slicing mode ...
Page 62
... The fixed peak detector input delay is equal – – – 4-18 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver –23 – 1); when cleared, is selects the local unit –23 – 1 – D[3] D[2] Conexant Bt8970 1 0 D[1] D[0] 100101B ...
Page 63
... Bt8970 Single-Chip HDSL Transceiver 0x3C—Digital AGC Modes Register (dagc_modes – – – eq_error_ Equalizer Error Adaptation—Read/write control bit that selects between the equalizer-error adaptation adaptation mode when set, and the self-adaptation mode when cleared. Equalizer error adaptation uses the equalizer error signal produced by the slicer as the DAGC error input signal. In self adaptation, the value of the DAGC Target Register [dagc_target_low, dagc_target_high ...
Page 64
... The meter register is automatically loaded at the end of each countdown interval D[7] D[6] D[5] 4-20 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver – zero_output zero_coefficients D[14] D[13] D[12] D[22] D[21] D[20 D[4] D[3] D[2] Conexant Bt8970 1 0 adapt_ adapt_gain coefficients 1 0 D[11] D[10] D[19] D[18 D[1] D[0] 100101B ...
Page 65
... Bt8970 Single-Chip HDSL Transceiver 0x44, 0x45—DC Level Meter Register (dc_meter_low, dc_meter_high) A 2-byte read-only register containing the 16 MSBs of the 32-bit, 2’s-complement DC-level meter accumulator. This meter sums the value of the receive signal input path—after format conversion and DC offset correction but before echo cancellation— ...
Page 66
... Meter Timer countdown interval. No increment occurs when a plus-three or minus-three symbol (+3, –3) is detected. The meter register is automatically loaded at the end of each countdown interval D[7] D[6] D[5] 4-22 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver D[4] D[3] D[2] D[12] D[11] D[10 D[4] D[3] D[2] D[12] D[11] D[10 D[4] D[3] D[2] Conexant Bt8970 1 0 D[1] D[0] D[9] D[ D[1] D[0] D[9] D[ D[1] D[0] 100101B ...
Page 67
... Bt8970 Single-Chip HDSL Transceiver 0x50, 0x51—Noise Level Meter Register (nlm_low, nlm_high) A 2-byte read-only register containing 16 MSBs of the 32-bit unsigned noise-level meter accumulator. This meter sums the absolute value of the detector’s slicer-error signal over each Meter Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read the low byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5F) ...
Page 68
... DFE coefficient within two symbol periods. Does not affect the value of the access data register – D[6] D[5] 4-24 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver D[4] D[3] D[ D[4] D[3] D[ D[4] D[3] D[ D[4] D[3] D[2] Conexant Bt8970 1 0 D[1] D[ D[1] D[ D[1] D[ D[1] D[0] 100101B ...
Page 69
... Bt8970 Single-Chip HDSL Transceiver 0x76—Scratch Pad Read Tap Select (sp_tap_select_read) A 6-bit read/write register representing an unsigned binary address defined over a range decimals. When written, it causes the selected 8-bit scratch pad memory location to be subsequently loaded into the lowest-order bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F] within two symbol periods. ...
Page 70
... EP Coefficients 0–4 EP Data Taps 0–4 DAGC Gain - Least-Significant Word DAGC Gain - Most-Significant Word DAGC Output FFE Output DAGC Input FFE Output, Delayed 1 Symbol Period DAGC Error Signal Equalizer Error Signal Slicer Error Signal Reserved D[4] D[3] D[ D[4] D[3] D[2] Conexant Bt8970 1 0 D[1] D[ D[1] D[0] 100101B ...
Page 71
... Bt8970 Single-Chip HDSL Transceiver 0x7B—Equalizer Microcode Write Select Register (eq_microcode_add_write) A 6-bit read/write register representing an unsigned binary address defined over a range decimals. When written, it causes all 32 bits of the Access Data Register [access_data_byte[3:0]; 0x7C–0x7F subsequently written to the selected equalizer microprogram store location within two symbol periods. Does not affect the value of the access data register ...
Page 72
... Register 4-28 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver Conexant Bt8970 100101B ...
Page 73
Electrical & Mechanical Specifications 5.1 Absolute Maximum Ratings Stresses above those listed may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those listed ...
Page 74
... Capacitive loading over which all digital output switching characteristics are guaranteed. 2. Still-air temperature range over which all electrical characteristics and timing requirements/characteristics are guaranteed. 5-2 Preliminary Information/Conexant Proprietary and Confidential Minimum 4.75 3.0 4.75 4.75 2.0 –0.3 0.8*V DD2 –0.3 — (1) –40 (2) Conexant Bt8970 Single-Chip HDSL Transceiver Typical Maximum Units 5.0 5.25 V 3.3 3.6 V 5.0 5.25 V 5.0 5.25 V — ...
Page 75
... Bt8970 Single-Chip HDSL Transceiver 5.3 Electrical Characteristics Typical characteristics measured at nominal operating conditions DD/AA operating conditions: min Table 5-3. Electrical Characteristics Symbol Parameter V High-Level Output Voltage @ Low-Level Output Voltage @ I OLL OL V Low-Level Output Voltage @ Input Leakage Current @ V I SS2 ...
Page 76
... QCLK QCLK QCLK (1) QCLK QCLK T 2 – HCLK HCLK T 2 – HCLK HCLK Conexant Bt8970 Units 100101_013 Maximum Units T 64 — QCLK T 16 — QCLK T 32 — QCLK HCLK HCLK ...
Page 77
... Bt8970 Single-Chip HDSL Transceiver Table 5-6. Symbol Clock (QCLK) Switching Characteristics Symbol Parameter 9 QCLK Period (T ) (1) QCLK 10 QCLK Pulse-Width High 11 QCLK Pulse-Width Low 12 QCLK Hold after HCLK Rising Edge 13 QCLK Delay after HCLK High ( 16, 32 according to hclk_freq[1,0]. QCLK can be frequency locked to the incoming data symbol rate. ...
Page 78
... RQ[1,0] Hold after QCLK Rising Edge 17 RQ[1,0] Delay after QCLK High Figure 5-3. Channel Unit Interface Timing, Parallel Master Mode RQ[1,0] QCLK TQ[1,0] 5-6 Preliminary Information/Conexant Proprietary and Confidential Parameter Parameter Conexant Bt8970 Single-Chip HDSL Transceiver Minimum Maximum Units 100 — — ns Minimum Maximum Units –50 — ...
Page 79
... Bt8970 Single-Chip HDSL Transceiver Table 5-9. Channel-Unit Interface Timing Requirements, Parallel Slave Mode Symbol 18 TBCLK, RBCLK Period (1) 19 TBCLK RBCLK Pulse-Width High , 20 TBCLK RBCLK Pulse-Width Low , 21 TQ[1,0] Setup prior to TBCLK Active Edge 22 TQ[1,0] Hold after TBCLK High/Low NOTE(S): (1) TBCLK and RBCLK must be frequency locked to QCLK though they may have independent phase relationships to QCLK and to one another ...
Page 80
... RDAT, QCLK Hold after BCLK Rising Edge 33 RDAT, QCLK Delay after BCLK High 5-8 Preliminary Information/Conexant Proprietary and Confidential Parameter Parameter Conexant Bt8970 Single-Chip HDSL Transceiver 20 100101_016 Minimum Maximum Units 100 — — ns Minimum Maximum Units — ...
Page 81
... Bt8970 Single-Chip HDSL Transceiver Figure 5-5. Channel Unit Interface Timing, Serial Mode HCLK 31 30 BCLK 33 32 QCLK RDAT 25 TDAT 100101B Preliminary Information/Conexant Proprietary and Confidential 5.0 Electrical & Mechanical Specifications Conexant 5.5 Channel Unit Interface Timing 29 100101_017 5-9 ...
Page 82
... Preliminary Information/Conexant Proprietary and Confidential Minimum 30 12 (1) 20 (2) (3,4) –27 0.5*Tmclk +25 0.5*Tmclk +25 ( Conexant Bt8970 Single-Chip HDSL Transceiver Maximum Units — ns — — ns — ns — ns — ns — ns — — ...
Page 83
... Bt8970 Single-Chip HDSL Transceiver Table 5-14. Microcomputer Interface Switching Characteristics Symbol Parameter 49 Data Out Enable (Low Z) after Read Strobe Falling Edge 50 Data Out Valid after Read Strobe Low 51 Data Out Hold after Read Strobe Rising Edge 52 Data Out Disable (High Z) after Read Strobe High ...
Page 84
... Strobe 34 ALE READY Figure 5-7. MCI Write Timing, Motorola Mode (MOTEL = 1) Address AD[7:0] or ADDR[7: Write Strobe R/W 34 ALE READY 5-12 Preliminary Information/Conexant Proprietary and Confidential Data (Input Data (Input Conexant Bt8970 Single-Chip HDSL Transceiver 45 100101_018 45 100101_019 100101B ...
Page 85
... Bt8970 Single-Chip HDSL Transceiver Figure 5-8. MCI Read Timing, Intel Mode (MOTEL = 0) AD[7:0] Address or ADDR[7: Read Strobe 34 ALE READY 100101B Preliminary Information/Conexant Proprietary and Confidential 5.0 Electrical & Mechanical Specifications Data (Output Conexant 5.6 Microcomputer Interface Timing 52 46 100101_020 5-13 ...
Page 86
... Electrical & Mechanical Specifications 5.6 Microcomputer Interface Timing Figure 5-9. MCI Read Timing, Motorola Mode (MOTEL = 1) AD[7:0] Address or ADDR[7: Read Strobe R/W 34 ALE READY 5-14 Preliminary Information/Conexant Proprietary and Confidential Data (Output Conexant Bt8970 Single-Chip HDSL Transceiver 52 46 100101_021 100101B ...
Page 87
... Bt8970 Single-Chip HDSL Transceiver Figure 5-10. Internal Write Timing Write Strobe IRQ Internal Register Internal RAM Access Data Register 5.6.1 Test and Diagnostic Interface Timing Table 5-15. Test and Diagnostic Interface Timing Requirements Symbol 63 TCK Pulse-Width High 64 TCK Pulse-Width Low 65 TMS, TDI Setup prior to TCK Rising Edge ...
Page 88
... TDO 69 TCK 65 TDI TMS Figure 5-12. SMON Timing HCLK 72 71 SMON 5-16 Preliminary Information/Conexant Proprietary and Confidential Parameter (1) (1) (1) (2) ). QCLK Conexant Bt8970 Single-Chip HDSL Transceiver Minimum Maximum Units 0 — ns — — ns — — ns — 100101_023 100101_024 100101B ...
Page 89
... Bt8970 Single-Chip HDSL Transceiver 5.6.2 Analog Specifications Table 5-17. Receiver Analog Requirements and Specifications Parameter Input Signals Input Voltage Range Input Resistance Common Mode Voltage Variable Gain Amplifier (VGA) Gain Step Gain Error Analog-to-Digital Converter Output Symbol Rate (F ) QCLK Differential Voltage Range (Full Scale ...
Page 90
... –0.01 –1. –0.16 –0.6T 0.5T 5-18 Preliminary Information/Conexant Proprietary and Confidential Comments 5-13 135 135 , 0dB gain setting QCLK 1/F QCLK Conexant Bt8970 Single-Chip HDSL Transceiver Mi Typ Max Units n 200 — 584 kHz — — — — 13. — 14.0 dBm 4 0.1 0.20 0. — ...
Page 91
... Bt8970 Single-Chip HDSL Transceiver Table 5-19. Transmitted Pulse Template Normalized Level A 0.01 0.0264 B 1.07 2.8248 C 1.00 2.6400 D 0.93 2.4552 E 0.03 0.0792 F –0.01 –0.0264 G –0.16 –0.4224 H –0.05 –0.1320 5.6.3 Test Conditions Figure 5-14. Transmitter Test Circuit 1 k TXPSP (67 TXPSN (68) 16.2 16.2 Transformer NOTE(S): See Table 4-20 for C8 and transformer values. ...
Page 92
... Figure 5-15. Standard Output Load (Totem Pole and Three-State Outputs) From Bt8970 Figure 5-16. Open-Drain Output Load (IRQ) From Bt8970 5-20 Preliminary Information/Conexant Proprietary and Confidential Data Rate 784 kbps 680 pF 3.0 mH IOL 1 IOH DD2 Conexant Bt8970 Single-Chip HDSL Transceiver 1168 kbps 470 pF 2.0 mH 100101_027 100101_028 100101B ...
Page 93
... Bt8970 Single-Chip HDSL Transceiver 5.7 Timing Measurements Figure 5-17 Figures 5-18 and 5-19. Figure 5-17. Input Waveforms for Timing Tests 3 V Input High Figure 5-18. Output Waveforms for Timing Tests VDD 2.4 V Output High 100101B Preliminary Information/Conexant Proprietary and Confidential 5.0 Electrical & Mechanical Specifications illustrates input waveforms. Output waveforms are displayed in 2 ...
Page 94
... Electrical & Mechanical Specifications 5.7 Timing Measurements Figure 5-19. Output Waveforms for Three-state Enable and Disable Tests 1.5 V Output Disabled 5-22 Preliminary Information/Conexant Proprietary and Confidential V OH 1 Output Output Disabled Enabled Conexant Bt8970 Single-Chip HDSL Transceiver - 0 0.2 V 100101_031 100101B ...
Page 95
... Bt8970 Single-Chip HDSL Transceiver 5.8 Mechanical Specifications Figure 5-20. 100-Pin Plastic Quad Flat Pack (PQFP) 100101B Preliminary Information/Conexant Proprietary and Confidential 5.0 Electrical & Mechanical Specifications 5.8 Mechanical Specifications Conexant 100101_032 5-23 ...
Page 96
... Electrical & Mechanical Specifications 5.8 Mechanical Specifications 5-24 Preliminary Information/Conexant Proprietary and Confidential Single-Chip HDSL Transceiver Conexant Bt8970 100101B ...
Page 97
Further Information Europe North – England literature@conexant.com Phone: +44 1344 486444 (800) 854-8099 (North America) Fax: (949) 483-6996 (International) Printed in USA Europe – Israel/Greece Phone: +972 9 9524000 World Headquarters Fax: Conexant Systems, Inc. Europe South – France 4311 ...