bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 34

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

2.0 Functional Description
2.5 Microcomputer Interface
2.5 Microcomputer Interface
The microcomputer interface provides operational mode control and status through internal registers. A
microcomputer write sets the operating modes to the appropriate registers. A read to a register verifies the
operating mode or provides the status. The microcomputer interface can be programmed to generate an interrupt
on certain conditions.
2.5.1 Source Code
Rockwell provides portable C-source code under a no-cost licensing agreement. This source code provides a
startup procedure, as well as diagnostic and system monitoring functions.
2.5.2 Microcomputer Read/Write
The microcomputer interface uses either an 8-bit-wide multiplexed address-data bus (Intel-style), or an
8-bit-wide data bus and another separate 8-bit-wide address bus (Motorola-style) for external data
communications. The interface provides access to the internal control and status registers, coefficients, and
microcode RAM. The interface is compatible with Intel or Motorola microcomputers, and is configured with
the inputs, MOTEL and MUXED. MOTEL low selects Intel-type microcomputer and control signals: ALE, CS,
RD, and WR. MOTEL high selects Motorola-type microcomputer and control signals: ALE, CS, DS, and R/W.
MUXED high configures the interface to use the multiplexed address-data bus with both the address and data
on the AD[7:0] pins. MUXED low configures the interface to use separate address and data bused with the data
on the AD[7:0] pins and the address on the ADDR[7:0] pins. The READY pin is provided to indicate when the
Bt8970 is ready to transfer data and can be used by the microcomputer to insert wait states in read or write
cycles.
configuration, control, status, and monitoring capabilities. Meter values are read lower-byte then upper-byte.
When the lower-byte is read, the upper-byte is latched at the corresponding value. This ensures that multiple
byte values correspond to the same reading. Most information can be directly read or written; however, the filter
coefficients require an indirect access.
2.5.2.1 RAM Access Registers
The internal RAMs of the transmit filter, LEC, NEC, DFE, equalizer, and microcode are accessed indirectly.
They all share a common data register which is used for both read and write operations, Access Data Register
[access_data_byte[3:0]; [0x7C–0x7F]. Each RAM has an individual read select and write select register. These
registers specify the location to access and trigger the actual RAM read or write.
select register. Two symbol periods afterwards, the individual bytes of that location are available for reading
from the Access Data Register.
affected RAM location is then written to the corresponding write tap select register. When writing the same
value to multiple locations, it is not necessary to rewrite the Access Data Register.
synchronous to the symbol clock. This has the effect of limiting access to these internal RAMs to one every
other cycle.
values will correspond to the same state.
2-16
The microcomputer interface provides access to a 256-byte internal address space. These registers provide
To perform a read, the address of the desired RAM location is first written to the corresponding read tap
To perform a write, the value to be written is first stored in the Access Data Register. The address of the
To assure reliable access to the embedded RAMs, internal read and write operations are performed
When reading or writing multiple filter coefficients, it may be desirable to freeze adaptation so that all
Preliminary Information/Conexant Proprietary and Confidential
Conexant
Single-Chip HDSL Transceiver
100101B
Bt8970