bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 35

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

Bt8970
Single-Chip HDSL Transceiver
2.5.2.2 Multiplexed Address/Data Bus
The timing for a read or write cycle is stated explicitly in the Electrical and Mechanical Specifications section.
During a read operation, an external microcomputer places an address on the address-data bus which is then
latched on the falling edge of ALE. Data is placed on the address-data bus after CS, RD, or DS go low. The read
cycle is completed with the rising edge of CS, RD, or DS.
microcomputer places data on the address-data bus after CS, WR, or DS go low. Motorola MCI will have R/W
falling edge preceding the falling edge of CS and DS. The rising edge of R/W will occur after the rising edge of
CS and DS. Data is latched on the address-data bus on the rising edge of WR or DS.
2.5.2.3 Separated Address/Data Bus
The timing for a read or write cycle using the separated address and data buses is essentially the same as over
the multiplexed bus. The one exception is that the address must be driven onto the ADDR[7:0] bus rather than
the AD[7:0] bus.
2.5.3 Interrupt Request
The twelve interrupt sources consist of: eight timers, a far-end signal high alarm, a far-end signal low alarm, a
SNR alarm, and a scrambler synchronization detection. All of the interrupts are requested on a common pin,
IRQ. Each interrupt may be individually enabled or disabled through the Interrupt Mask Registers
[mask_low_reg, mask_high_reg; 0x02, 0x03]. The cause of an interrupt is determined by reading the Timer
Source Register [timer_source; 0x04] and the IRQ Source Register [irq_source; 0x05].
while the alarm is active. In other words, it cannot be cleared while the condition still exists.
common interrupt request.
2.5.4 Reset
The reset input (RST) is an active-low input that places the transceiver in an inactive state by setting the mode
bit (0) in the Global Modes and Status Register [global_modes; 0x00]. An internal supply monitor circuit
ensures that the transceiver will be in an inactive state upon initial application of power to the chip.
2.5.5 Registers
The Bt8970 has many directly addressable registers. These registers include control and monitoring functions.
Write operations to undefined registers will have unpredictable effects. Read operations from undefined
registers will have undefined results.
2.5.6 Timers
Eight timers are integrated into the Bt8970 to control the various on-chip meters and to aid the microcomputer
in stepping through the events of the startup sequence.
when the counter is reloaded or decremented.
100101B
A write operation latches the address from the address-data bus at the falling edge of ALE. The
The timer interrupt status is set only when the timer transitions to zero. Alarm interrupts cannot be cleared
IRQ is an open-drain output and must be tied to a pull-up resistor. This allows IRQ to be tied together with a
The structure of each timer includes down counter, zero detect logic, and control circuitry, which determines
Preliminary Information/Conexant Proprietary and Confidential
Conexant
2.0 Functional Description
2.5 Microcomputer Interface
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