bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 64

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

4.0 Register
0x3E—Error Predictor Modes Register (ep_modes)
zero_output
zero_coefficients
adapt_coefficents
adapt_gain
0x40, 0x41—Phase Detector Meter Register (pdm_low, pdm_high)
A 2-byte read-only register containing the 16 MSBs of the 26-bit, 2’s-complement phase detector meter
accumulator. This meter sums the output of the timing recovery module’s phase detector—prior to being offset
by the Phase Offset Register [pll_phase_offset_low, pll_phase_offset_high; 0x24, 0x25]—over each Meter
Timer countdown interval. Automatically loaded at the end of each interval, the meter register must be read low
byte first, followed by high byte, unseparated by any other meter access (addresses 0x40 to 0x5F).
0x42—Overflow Meter Register (overflow_meter)
A single-byte read-only register containing all 8 bits of the unsigned overflow meter accumulator. This meter
counts the number of ADC overflow conditions which occur during each Meter Timer countdown interval,
limited to a maximum count of 255 (0xFF). The meter register is automatically loaded at the end of each
countdown interval.
4-20
D[17]
D[25]
D[7]
7
–
7
7
Zero Output—Read/write control bit which, when set, zeros the error predictor correction
signal before subtraction from the input signal. Achieves the affect of disabling, or bypassing,
the error predictor function. Does not disable coefficient adaptation. When cleared, normal
error predictor operation is performed.
Zero Coefficients—Read/write control bit which, with coefficient adaptation enabled
(adapt_coefficients = 1), continuously zeros all coefficients when set; allows normal
coefficient updates when cleared. If coefficient adaptation is disabled (adapt_coefficients = 0),
this control bit has no affect. This behavior differs slightly from the similar function
(zero_coefficients) of the LEC, NEC, and DFE filters.
Adapt Coefficients—Read/write control bit enables coefficient adaptation when set;
disables/freezes adaptation when cleared. Coefficient values are preserved when adaptation is
disabled.
Adaptation Gain—Read/write control bit specifies the adaptation gain. When set, the
adaptation gain is four times higher than when cleared.
D[16]
D[24]
D[6]
6
6
6
–
Preliminary Information/Conexant Proprietary and Confidential
D[15]
D[23]
D[5]
5
–
5
5
D[14]
D[22]
D[4]
4
4
4
–
Conexant
zero_output
D[13]
D[21]
D[3]
3
3
3
zero_coefficients
D[12]
D[20]
D[2]
2
2
2
Single-Chip HDSL Transceiver
coefficients
adapt_
D[11]
D[19]
D[1]
1
1
1
adapt_gain
D[10]
D[18]
100101B
D[0]
Bt8970
0
0
0