bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 62

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

4.0 Register
two_level
lfsr_lock
htur_lfsr
descr_on
0x3B—Peak Detector Delay Register (peak_detector_delay)
A 4-bit read/write register interpreted as an unsigned binary number. Specifies a number of additional symbol
delays inserted in the peak detector input path of the symbol detector. Must be set to a value that equalizes the
total path delay in each of the peak detector and slicer input paths according to the following formula: peak
detector delay register value = DAGC delays + FFE delays – fixed peak detector input delays. The DAGC and
FFE delays are not fixed, but result from the microprogrammed implementation of these functions. If used
unmodified, they equal 0 and 7, respectively. The fixed peak detector input delay is equal to 3.
4-18
7
–
Two-Level Mode—Read/write control bit that selects two-level mode when set, four-level
mode when cleared. Affects the slicer and the scrambler/descrambler function. In two-level
mode, the slicer uses a single threshold set at zero to recover sign bits only; all magnitude
information is lost. Scrambler/descrambler updates are slowed to the symbol rate (half the
normal bit rate) to process only sign information as well; all magnitude output bits are sourced
with a constant logic zero value producing two-level symbols constrained to +3 and –3 values.
In four-level mode, the slicer uses two thresholds derived from the Cursor Level Register
[cursor_level_low, cursor_level_high; 0x36–0x37], as well as the zero threshold, to recover
both sign and magnitude information. The scrambler/descrambler is updated at the full bit rate
to process both sign and magnitude bits as well.
LFSR Lock—Read/write control bit that enables the auto-scrambler synchronization mode
(lfsr_lock) in the detector when set; disables this mode when cleared. Affects the behavior of
the scrambler/descrambler function, overriding the descr_on setting. When enabled, the
scrambler/descrambler is forced into the descrambler mode for 23 cycles. It is then switched to
the scrambled-ones mode for 128 cycles. While in this mode, the outputs of the scrambler and
the slicer/peak detector are compared against one another. The number of equivalent bits
(equal comparisons) is accumulated and compared to the value of the Scrambler
Synchronization Threshold Register [scr_sync_th; 0x2E].
interrupt flag is set in the IRQ source register [irq_source; 0x05] and the process terminates
with the scrambler/descrambler left in the scrambled-ones mode. (The sync interrupt flag
cannot be cleared while lfsr_lock remains high.) After 128 cycles, if the threshold is not
exceeded, the accumulator is cleared, the scrambler/descrambler re-enters the descrambler
mode for another 23 cycles, and the process repeats until either sync is achieved or this mode
is disabled. Once disabled, the sync interrupt flag can be cleared (if active) and the
scrambler/descrambler returns to the mode specified by descr_on.
Remote Unit (HTU-R/NTU) Polynomial Select—Read/write control bit that selects one of two
feedback polynomials for the scrambler/descrambler. When set, this bit selects the remote unit
(HTU-R/NTU) receive polynomial (x
(HTU-C/LTU) polynomial (x
Descrambler/Scrambler Select—Read/write control bit that configures the
scrambler/descrambler function as a descrambler when set, and as a scrambler when cleared.
As a scrambler, this bit can only generate a scrambled-all-ones sequence (constant high
logic-level input); all incoming data is ignored. In the auto-scrambler synchronization mode
(lfsr_lock = 1), this selection is overwritten though the value of the control bit is unaffected.
At any time during the 128 cycles, if the count exceeds the threshold (greater than), the sync
6
–
Preliminary Information/Conexant Proprietary and Confidential
5
–
–23
4
–
Conexant
+ x
–18
–23
+ 1).
+ x
D[3]
–5
3
+ 1); when cleared, is selects the local unit
D[2]
2
Single-Chip HDSL Transceiver
D[1]
1
100101B
D[0]
Bt8970
0