bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 27

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

Bt8970
Single-Chip HDSL Transceiver
2.2.5.5 Microcoding
The DAGC, FFE, and EP filters are implemented using an internal microprogrammable Digital Signal
Processor (DSP) optimized for LMS filters. Internal DSP micro-instructions are stored in an on-chip RAM.
This microcode RAM is loaded after powerup through the microcomputer interface when the transceiver is
initialized.
2.2.6 Detector
The detector converts the equalized received signal into a 2B1Q symbol and produces two error signals used in
adapting the receiver equalizers. The signal detection uses two sub-blocks, a slicer, and a peak detector.
Additionally, the detector contains a scrambler and Bit Error Rate (BER) meter for use during the startup
sequence.
2.2.6.1 Slicer
The slicer thresholds the equalized signal to produce a 2B1Q symbol. The input to the slicer is the FFE output
minus the DFE and EP outputs.
startup when the only transmitted symbols are +3 or –3, the slicer threshold is set at zero.
complement number, but must be positive and less than 0x2AAA for proper operation.
2.2.6.2 Peak Detector (PKD)
The PKD is only used during the two-level transmission part of startup. It operates on the echo-free signal. A
signal is detected to be a +3 if it is higher than both of its neighbors, or a –3 if it is lower than both of its
neighbors. If neither of the peaked conditions exist, the output of the slicer is used.
2.2.6.3 Error Signals
The detector computes two error signals for use in the equalizer: a 16-bit slicer and a 16-bit equalizer.
2.2.6.4 Scrambler Module
The scrambler may operate as either a scrambler or as a descrambler. The scrambler block is used during the
scrambled-ones part of the startup sequence. This provides an error-free signal for equalizer adaptation. This
scrambler is essentially a 23-bit-long Linear Feedback Shift Register (LFSR) with feedback. The feedback point
depends on whether the transceiver is being used in a central-office or remote-terminal application.
stream, as shown in
Table 2-4. Two-Level Symbol-to-Bit Conversion
100101B
The slicer can operate in two modes: two-level and four-level. In the two-level mode, used during the part of
When in four-level mode, the cursor level is specified via the microcomputer interface. It is a 16-bit, 2s
When operating as a descrambler, the input source is the detector output. The symbol is converted to a bit
Table 2-4
Input Symbol
Preliminary Information/Conexant Proprietary and Confidential
–3
+3
for the two-level case.
Conexant
Output Bit
0
1
2.0 Functional Description
2.2 Receive Section
2-9