bt8970 Mindspeed Technologies, bt8970 Datasheet - Page 57

• Manufacturer Part Number: bt8970
• Description: Single-chip Hdsl Transceiver
• Manufacturer: Mindspeed Technologies

Bt8970
Single-Chip HDSL Transceiver
0x22—PLL Modes Register (pll_modes)
clk_freq[1,0]
phase_detector_
gain[1,0]
freeze_pll
pll_gain[1,0]
100101B
clk_freq[1]
7
clk_freq[0]
Clock Frequency Select—Read/write binary field specifies one of four data rate ranges for
Bt8970 operation. The “00” state is automatically selected by RST assertion and upon initial
power application. The crystal or external clock frequency must be equal to 8 times the data
rate.
Phase Detector Gain—Read/write binary field specifies one of four gain settings for the
timing-recovery phase detector function.
Freeze PLL—Read/write control bit. When set, this bit zeros the proportional term of the loop
compensation filter and disables accumulator updates causing the PLL to hold its current
frequency. When cleared, proportional term effects and accumulator updates are enabled
allowing the PLL to track the phase of the incoming data.
PLL Gain—Read/write binary field specifies the gain (proportional and integral coefficients)
of the loop compensation filter.
6
pll_gain[1:0]
Preliminary Information/Conexant Proprietary and Confidential
phase_detector_gain[1,0]
00
01
10
11
negate_symbol
5
clk_freq[1,0]
00
01
10
11
00
01
10
11
phase_detector_
gain[1]
4
Proportional Coefficients
Conexant
Normalized
phase_detector_
16
64
1
4
gain[0]
3
freeze_pll
2
Data Rate Range
Normalized Gain
968 to 1368 kbps
Above 1368 kbps
656 to 968 kbps
160 to 656 kbps
Reserved
Integral Coefficients
pll_gain[1]
1
2
4
Normalized
1
4096
256
32
1
4.0 Register
pll_gain[0]
0
4-13