ox16pci958 Oxford Electrical Products, ox16pci958 Datasheet - Page 28

• Manufacturer Part Number: ox16pci958
• Description: Octal Uart With Interface
• Manufacturer: Oxford Electrical Products

OXFORD SEMICONDUCTOR LTD.
4.7.1. Auto-RTS
Auto-RTS attempts to control the flow of serial
data in to the UART. When enabled, it
automatically signals to a connected device that
it should stop transmitting, because there is a
risk of the receive FIFO overrunning. This is
done by making the state of the RTS# output
dependent on the level of the receive FIFO:
RTS# is asserted when the receive FIFO is
below a certain trigger level, and deasserted
when the receive FIFO is at or above that trigger
level. The OX16PCI958 UARTs support the
setting of the trigger level to four predefined
levels using FCR7:6 and also allow a precise
value to be set using RFTR.
4.7.2. Auto-CTS
Auto-CTS controls the flow of serial data from
the UART. When enabled, the transmitter will
not start transmitting a new data byte unless the
CTS# input is asserted. If data transmission is
stopped in this way, it restarts as soon as CTS#
is asserted. The UART never sends partial data
bytes.
4.7.3. Enabling Auto-RTS & Auto-CTS
It is possible to have neither auto-RTS nor auto-
CTS enabled (with manual control of RTS#), or
both enabled, or auto-CTS enabled with RTS#
held deasserted. Auto-RTS and auto-CTS are
activated by setting bits MCR5 and MCR1, but
auto flow control is also affected by MCR1,
MCR4, and UCR0.
Clock Prescaler Register (CPR)
This register allows more fine-grained control
over the baud rate than is possible using the
divisor alone. Before being divided by the divisor
value stored in DLL and DLM, the clock is
prescaled, being divided by (CPR/8). Valid
values of the CPR are 8 to 255 inclusive. The
reset value of the CPR is 8, i.e. the prescaler
has no effect. This register is automatically set
to 8, 16 32 or 64 when the PCR is written.
DS-0022 Nov 05
External—Free Release
Synchronization Factor Register (SFR)
The UART uses an internal clock that is faster
(by a fixed integer factor) than the baud rate
selected. The factor by which it is faster is called
the synchronisation factor (SF). Received data
is clocked into the UART every SF clock cycles,
and the position of these enabled cycles is
selected so as to clock in data from as close to
the middle of each serial bit as possible. A
higher value of SF gives a sampling time which
is closer to the centre of the bits, and hence
gives greater tolerance of line noise, but also
gives higher power consumption and a lower
maximum baud rate.
This register allows the programmer to select
the synchronisation factor used. Allowed values
for writing to this register are 04h, 08h, and 10h.
Programmable Baud Rate Generator
The internal clock used by the UART transmit
and receive units is generated by taking the
clock input fed into XTALI and dividing it first by
the global clock divider, then by a prescaling
factor, and then by a 16-bit integer value (the
“divisor”). The baud rate calculation is:
baud rate =
XTALI input freq (global predivider x (CPR/8) x divisor x SF)
The divisor is stored in two 8-bit divisor latches.
Setting the divisor latches is a necessary step in
the initialization of the UART before data can be
transmitted or received.
Loading a divisor of zero (all bits cleared in DLL
and DLM) stops the clocking of the receiver and
transmitter, i.e. it gives a baud rate of zero. No
serial data is transmitted or received, no data
enters the receive FIFO or leaves the transmit
FIFO. The level on SOUT can still be changed
by writing LCR6, and all other UART functions
continue to operate.
Port Control Register (PCR)
Bit 3 allows the CTS input of the UART to be
held in a ‘true’ state, regardless of the state of
the CTS# input pin: see Table 26.
Value
0
1
Table 26 Hold CTS Values
Description
CTS reflects state of CTS# pin
CTS held true
OX16PCI958 DATA SHEET
Page 28